Abstract: An embodiment generates a composite high speed clock with embedded frame synchronization using simple digital encoding of a high speed reference clock. The high speed reference clock and self-aligned frame synchronization signal are recovered by standard logic gate circuitry. The encoding and decoding circuits are comprised of basic digital logic gates with low propagation delay skew and timing jitter. The encoded clock is easier to transmit from source unit to destination unit over common transmission media (i.e., digital transceivers, amplifiers, splitters, connectors and coaxial cable) because only a single interface is required and because the encoding scheme reduces the composite clock to a minimal transmission bandwidth with constrained waveform harmonic content, relative to a low frequency frame sync with fast rise time that requires a broadband transmission media.

Abstract: A digital automatic level control system employs delay elements, which enable information about a signal parameter from the past, present and future to be processed to provide an optimal gain that can be used to level rapidly varying signals, such as bursty signals. As digital time samples of a signal are passed through first and second buffers, first and second accumulators maintain running sums that are related to the sum of the samples presently in the first and second buffers, respectively. The sums in the first and second accumulators represent information about the signal parameter for the future and the past, respectively. By choosing the maximum of these two values, the system can anticipate the beginning of a signal burst, and still have enough delay to compensate the end of a signal burst. In one embodiment of the invention, multiple channel signals can be leveled, either individually or in groups.

Abstract: A digital automatic level control system employs delay elements, which enable information about a signal parameter from the past, present and future to be processed to provide an optimal gain that can be used to level rapidly varying signals, such as bursty signals. As digital time samples of a signal are passed through first and second buffers, first and second accumulators maintain running sums that are related to the sum of the samples presently in the first and second buffers, respectively. The sums in the first and second accumulators represent information about the signal parameter for the future and the past, respectively. By choosing the maximum of these two values, the system can anticipate the beginning of a signal burst, and still have enough delay to compensate the end of a signal burst. In one embodiment of the invention, multiple channel signals can be leveled, either individually or in groups.