Patents by Inventor Cyrus Afghahi
Cyrus Afghahi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8749011Abstract: In one embodiment, a die arrangement is disclosed in which a wire-bond pad may be operatively coupled to a power supply via a wire bond. A first pad may be operatively coupled to the wire-bond pad. A second pad may be operatively coupled to the first pad via a redistribution layer.Type: GrantFiled: April 26, 2005Date of Patent: June 10, 2014Assignee: Broadcom CorporationInventors: Matthew Kaufmann, Morteza Cyrus Afghahi
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Publication number: 20140047296Abstract: A memory system provides Error Correcting Code (ECC) protection for data stored in a parity enabled memory. The memory may include designated parity locations for data stored in the memory. During write operations, the system may obtain data to write into the memory, compute ECC protection bits for the data, and store the ECC protection bits in locations in the memory designated as parity locations for the data. During read operations, the system may read data from the memory. The system may also read protection bits for the data from locations designated as parity locations for the data. Then, the system may interpret the protection bits as ECC protection bits instead of as parity bits. The system may provide ECC protection for data without additional overhead or memory configuration changes to the parity enabled memory.Type: ApplicationFiled: August 9, 2012Publication date: February 13, 2014Applicant: Broadcom CorporationInventors: Iraj Motabar, Morteza Cyrus Afghahi
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Patent number: 8164362Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.Type: GrantFiled: March 8, 2004Date of Patent: April 24, 2012Assignee: Broadcom CorporationInventors: Morteza Cyrus Afghahi, Esin Terzioglu
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Patent number: 8004912Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.Type: GrantFiled: June 25, 2009Date of Patent: August 23, 2011Assignee: Broadcom CorporationInventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
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Patent number: 7889553Abstract: A non-volatile memory cell includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; and a programming line coupled to the control gate.Type: GrantFiled: April 24, 2008Date of Patent: February 15, 2011Assignee: Novelics, LLC.Inventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
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Patent number: 7751225Abstract: In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node.Type: GrantFiled: January 18, 2008Date of Patent: July 6, 2010Assignee: Novelics, LLCInventors: Gil I. Winograd, Morteza Cyrus Afghahi, Esin Terzioglu
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Patent number: 7738308Abstract: In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal.Type: GrantFiled: January 18, 2008Date of Patent: June 15, 2010Assignee: Novelies, LLCInventors: Morteza Cyrus Afghahi, Esin Terzioglu, Gil I. Winograd
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Patent number: 7715262Abstract: In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors that have a relatively thin gate oxide; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein each memory cell includes an access transistor coupled to a storage cell, the access transistor having a relatively thick gate oxide, whereby the storage capacitor is capable of being charged to a VIO power supply voltage that is greater than a VDD power supply voltage for the core transistors.Type: GrantFiled: June 27, 2008Date of Patent: May 11, 2010Assignee: Novelics, LLCInventors: Morteza Cyrus Afghahi, Esin Terzioglu, Gil I. Winograd, Melinda L. Miller
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Patent number: 7710811Abstract: In one embodiment, a memory is provided that includes: a plurality of memory cells arranged in columns, each column coupled to a corresponding bit line; a sense amplifier adapted to sense the voltage on a pair of the bit lines to determine a binary state of an accessed memory cell coupled to a first one of the bit lines in the pair; and a first trim capacitor having a first terminal directly coupled to one of the bit lines in the pair, the first trim capacitor having an opposing second terminal coupled to a first trim capacitor signal, the memory being adapted to change a voltage of the first trim capacitor signal while the sense amplifier senses the voltage to determine the binary state of the accessed memory cell.Type: GrantFiled: January 18, 2008Date of Patent: May 4, 2010Assignee: Novelics, LLCInventors: Esin Terzioglu, Gil L Winograd, Morteza Cyrus Afghahi
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Patent number: 7710755Abstract: In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of memory cells arranged into rows and columns, wherein each memory cell comprises an access transistor coupled to a storage transistor, each access transistor being arranged in a rectangular shape having a length greater than a width, the length being aligned with a corresponding column, the access transistor coupling to a storage transistor having a width greater than the width of the rectangular shape, the access transistor having a length aligned with a corresponding row such that each memory cell is L-shaped, and wherein the L-shaped memory cells in each column are staggered with respect to neighboring columns such that the L-shaped memory cells in a given column are interlocked with the L-shaped memory cells in an adjacent column.Type: GrantFiled: January 24, 2008Date of Patent: May 4, 2010Assignee: Novelics, LLCInventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
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Publication number: 20090316512Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.Type: ApplicationFiled: June 25, 2009Publication date: December 24, 2009Inventors: Esin Terzioglu, Gil I. Winograd, Cyrus Afghahi
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Patent number: 7567482Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.Type: GrantFiled: December 27, 2006Date of Patent: July 28, 2009Assignee: Broadcom CorporationInventors: Esin Terzioglu, Gil I. Winograd, Cyrus Afghahi
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Patent number: 7554870Abstract: In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of rows of memory cells, each of the memory cell rows being arranged into columns, wherein each of the memory cell rows is crossed by a row of four word lines, and wherein each of the columns is crossed by a bit line; a plurality of sense amplifiers corresponding to the bit lines such that a single sense amplifier corresponds to every four bit lines; and a plurality of 4:1 multiplexers corresponding to the plurality of sense amplifiers, each 4:1 multiplexer coupling its corresponding sense amplifier to its corresponding four bit lines.Type: GrantFiled: January 24, 2008Date of Patent: June 30, 2009Assignee: Novelics, LLCInventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
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Patent number: 7508694Abstract: A one-time-programmable memory cell uses two complementary antifuses that are programmed in a complementary fashion such that only one of the two complementary antifuses is stressed by a programming voltage. The programming voltage stress one a particular one of the complementary antifuses indicates a logical state of the memory cell. For example, a logical high state may correspond to a first one of the complementary antifuses being stressed whereas a logical low state may correspond to the stressing of the remaining one of the complementary antifuses.Type: GrantFiled: May 11, 2007Date of Patent: March 24, 2009Assignee: Novelics, LLCInventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
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Publication number: 20090010041Abstract: In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors that have a relatively thin gate oxide; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein each memory cell includes an access transistor coupled to a storage cell, the access transistor having a relatively thick gate oxide, whereby the storage capacitor is capable of being charged to a VIO power supply voltage that is greater than a VDD power supply voltage for the core transistors.Type: ApplicationFiled: June 27, 2008Publication date: January 8, 2009Inventors: Morteza Cyrus Afghahi, Esin Terzioglu, Gil I. Winograd, Melinda L. Miller
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Publication number: 20080291728Abstract: A non-volatile memory cell is provided that includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; and a programming line coupled to the control gate.Type: ApplicationFiled: April 24, 2008Publication date: November 27, 2008Inventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
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Publication number: 20080266935Abstract: In one embodiment, a DRAM is provided that includes a plurality of memory cells, each memory cell including an access transistor and a storage capacitor, wherein the storage capacitor includes a first node coupled to the access transistor and a second node isolated from the first node, the second node comprising signal-bearing metal conductors.Type: ApplicationFiled: August 27, 2007Publication date: October 30, 2008Inventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
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Patent number: 7440311Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a second plate separated from the first plate by a fringe capacitance junction.Type: GrantFiled: September 28, 2006Date of Patent: October 21, 2008Assignee: Novelics, LLCInventors: Esin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
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Publication number: 20080225613Abstract: In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal.Type: ApplicationFiled: January 18, 2008Publication date: September 18, 2008Inventors: Morteza Cyrus Afghahi, Esin Terzioglu, Gil I. Winograd
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Publication number: 20080225568Abstract: In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node.Type: ApplicationFiled: January 18, 2008Publication date: September 18, 2008Inventors: Gil I. Winograd, Morteza Cyrus Afghahi, Esin Terzioglu