Abstract: A high-speed fiber optic star configuration network uses a processor at the network hub to monitor and control network activity. The hub and the individual nodes of the network cooperate to calibrate node transmitter power levels and node receiver sensitivities. A token passing protocol is used to allocate network access. The token passing is monitored at the hub to detect lost tokens or a babbling bus. The hub processor has the capability to initiate tokens or restore lost tokens and to shut off the transmitter of a node which remains connected to the bus for an excessive period of time. In one embodiment, the circuit elements of the hub are duplicated to provide two separate paths through the hub.

Abstract: A processing system (10) includes a backplane bus (13) that defines a plurality of locations (20-31) implemented as backplane slots each for connecting any option module (41) thereto. Each slot includes contact pins (201a-d) that carry binary logic levels forming a different digital number at each slot. Option modules include their own source of timing signals (220) comprising an oscillator (221) and an identical thermally-sensitive crystal (222) for driving the oscillator. Each option module includes receptacles (207a-d) for the contact pins. The receptacles are connected to the digital input port of a D/A converter (225) whose output port is connected to a heater (224) mounted in physical proximity to the crystal in the crystal's case (223). Depending on which slot an option module is mounted in, the D/A converter receives a different digital input and hence generates a different level of output.

Abstract: A multipoint access data communication system which includes a communication bus, a plurality of transceivers connected to the bus for communication, and a remote collision detector associated with each transceiver for detecting collisions between communications on the medium, has improvements which adapt the transceivers for connection to a plurality of network interface units, and local access arbitrators associated with the transceivers for preventing collisions between transmissions simultaneously attempted by two or more network interface units connected to a transceiver.

Abstract: A detection circuit for detecting a mismatch between the output signals of duplicated logic units (10a, 10b). The output terminals of one of the duplicated logic units are correspondingly connected to the output terminals of the other duplicated logic unit, while the power supply leads of the duplicated logic units (10a, 10b) are connected to a positive voltage source (32) through a current imbalance detector. Any mismatch between the output signals of the duplicated logic units (10a, 10b) will result in the detection of a large imbalance of current being supplied to the duplicated logic units (10a, 10b). Upon detection, the detector will generate an error signal.