Abstract: The encoder arrangement and bit-exact IDCT protocol provides methods and arrangements that prevent an accumulation of errors between a transmitting codec and a receiving codec. One example embodiment is directed to an arrangement for use in a first terminal for communicating representations of images with a second terminal using a communications channel on which communication has been established between the first terminal and the second terminal. The arrangement includes a processor-based decoder/encoder circuit and a bit-exact circuit. The processor-based decoder/encoder circuit is arranged to process video data using an inverse transformer loop. The bit-exact circuit prevents unacceptable accumulation of an error within the inverse transformer loop by using the inverse transformer in the loop according to a bit-exact specification between the encoder and decoder in the respective first and second terminals.