Abstract: An improved decision feedback phase lock loop having an erasure zone detector and a feedback loop interrupting switch responsive to the output of the erasure zone detector which cooperate to eliminate from the feedback loop those error signals corresponding to detected data falling within certain predetermined regions of the encoding constellation. The erasure zone detector compares the complex input signal to certain predetermined erasure zone reference signals so as to determine when the input signal falls within an erasure zone and correspondingly actuates the loop switch to prevent certain feedback error signals from being input to the loop filter.

Abstract: A complex ternary correlator and method for adaptive gradient computation in an adaptive equalizer and including four ternary operation circuits, four ternary multiplier circuits for obtaining the cross products of the ternary operation outputs, a subtractor circuit for developing a signal commensurate with the difference between two of the ternary multiplier outputs, an adder circuit for developing a signal commensurate with the sum of the remaining two ternary multiplier outputs and two identical integrating circuits for obtaining the real and imaginary adaptive tap coefficient update increments in an adaptive equalizer.

Abstract: A leaky digital integrator comprising an accumulator circuit including an adder having first and second adder input terminals and an adder output terminal, and a shift register coupling the adder output terminal back to the second adder input terminal and to an integrator output terminal; a ternary signal detection circuit coupled to the integrator output terminal and operative to develop one of three decay factor signals depending upon whether the integrator output signal level is above, equal to or below a predetermined reference level; and switching apparatus having a first switched terminal which is periodically coupled at a first rate to the first adder input terminal to input update data signals to the accumulator circuit and a second switched terminal which is periodically coupled at a second rate to the first adder input terminal to input decay data signals to the accumulator circuit such that the circuit as a whole performs according to the equationa.sub.i (t)=Da.sub.i (t-1)+.DELTA.a.sub.