Abstract: In one aspect, a method for measuring cell metabolism through photobiomodulation comprising steps of receiving a broadband near-infrared spectroscopy (bbNIRS) image including one or more responding signals to light stimulation regarding a specific cell; extracting two or more turning points on one of the responding signals; extracting two or more threshold points on one of the responding signals; generating a first line by curve fitting to approximate the turning points on the responding signal and determining a slop of the first line; generating a second line by curve fitting to approximate the threshold points on the responding signal and determining a slop of the second line; and comparing the input images, the first line and the second line to determine a rate of cell metabolism of the specific cell.

Abstract: A system for in vivo and transcranial stimulation of brain tissue of a subject may include at least one light source; a controller to control operation of the light source; a signal detecting unit and a processor configured to receive a signal from the signal detecting unit; analyze the signal and generate a feedback signal to the controller to control the light source until optimal results are obtained, wherein the detected signal is an electroencephalogram (EEG) signal, on which local peak frequencies are extracted and recorded periodically and repeatedly within a predetermined time frame before, during and after light stimulation, and the feedback signal is generated by comparing the local peak frequencies of before, during and after the brain stimulation to determine if brain synchronization occurs and sustains, and the feedback signal is generated.

Abstract: A method for identifying a body region in a medical image includes obtaining a medical image including a number of consecutive bio-section images, inputting the medical image into a preset machine learning model to obtain a numerical value for each of the bio-section images corresponding to the body region to which the bio-section image belongs, determining whether the numerical values of the medical image are abnormal, adjusting the numerical values when the numerical values are abnormal, determining the body region corresponding to the numerical values or the adjusted numerical values, and labeling the body region in the medical image and outputting the labeled medical image. The bio-section images are cross-sectional images of a living body.

Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.

Abstract: In one aspect, a system for in vivo and transcranial stimulation of brain tissue of a subject may include at least one light source, a controller to control operation of the light source, a signal detecting unit and a processor configured to receive signals from the signal detecting unit, analyze the signals and generate a feedback signal to the controller to control the light source until optimal results are obtained. In one embodiment, the light source is a laser instrument and the wavelength can range from 800 to 1100 nm. In another embodiment, the irradiance of the laser instrument can range from 50 to 1000 mW/cm2.

Abstract: A memory system includes a plurality of memory cells. A memory cell includes an anti-fuse transistor, a first select unit, and a second select unit. The anti-fuse transistor has a first terminal, a second terminal, and a control terminal coupled to an anti-fuse control line. The first select unit is coupled to the first terminal of the anti-fuse transistor, a first bit line, and an odd word line. The second select unit is coupled to the second terminal of the anti-fuse transistor, a second bit line, and an even word line. During a pre-screen operation of the memory cell, the odd word line and the even word line are at different voltages.

Abstract: A random bit cell includes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.

Abstract: A reference voltage generator includes an output terminal, a current source, a reference circuit, a protection circuit, and a control circuit. The output terminal outputs a reference voltage. The current source is coupled to the output terminal, and generates a reference current. The reference circuit is coupled to the output terminal, and generates a reference voltage according to the reference current. The protection circuit is coupled to the output terminal, and adjusts a voltage of the output terminal to an operating voltage. The control circuit is coupled to the reference circuit and the protection circuit. The control circuit controls the reference circuit and the protection circuit according to a start signal.

Abstract: A memory system includes a plurality of memory cells. A memory cell includes an anti-fuse transistor, a first select unit, and a second select unit. The anti-fuse transistor has a first terminal, a second terminal, and a control terminal coupled to an anti-fuse control line. The first select unit is coupled to the first terminal of the anti-fuse transistor, a first bit line, and an odd word line. The second select unit is coupled to the second terminal of the anti-fuse transistor, a second bit line, and an even word line. During a pre-screen operation of the memory cell, the odd word line and the even word line are at different voltages.

Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.

Abstract: Various arrangements for integrating control of multiple cloud-based smart-home devices are presented. Registration information may be received for a first and second smart-home device that are controlled using different cloud-based server systems. A determination may be made that that the first smart-home device and the second smart-home device share a common function. The first smart-home device and the second smart-home device may be assigned to a common operating characteristic group based on the common function being shared by the first smart-home device and the second smart-home device. A control element may be provided that allows for control of smart-home devices with the common operating characteristic group. The control element may control the common function at the first smart-home device via the first cloud-based server system and at the second smart-home device via the second cloud-based server system.

Abstract: A random bit cell incudes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.

Abstract: An apparatus comprises a memory slot mounted to a main board, an expansion slot mounted to the main board and electrically coupled to the memory slot, a backup power module receivable in the expansion slot, and a main power source electrically coupled to the expansion slot and the memory slot. During normal operation, the main power source supplies electrical power to the memory slot and charge the backup power module. In the event of power loss or main power source failure, the backup power module discharges electrical power to the memory slot.

Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.

Abstract: A sensing circuit includes a sensing stage. The sensing stage includes a voltage clamp, a P-type transistor and an N-type transistor. The voltage clamp receives a first power supply voltage and generates a second power supply voltage. The source terminal of the P-type transistor receives the second power supply voltage. The gate terminal of the P-type transistor receives a cell current from a selected circuit of a non-volatile memory. The drain terminal of the N-type transistor is connected with the drain terminal of the P-type transistor. The gate terminal of the N-type transistor receives a bias voltage. The source terminal of the N-type transistor receives a ground voltage. In a sensing period, the second power supply voltage from the voltage clamp is fixed and lower than the first power supply voltage.

Abstract: The invention relates to organic electroluminescent devices, and discloses a phosphorescence device containing heterocyclic phosphoric acid metal complexes. The phosphorescence device provided by the invention contains metal complexes of heterocyclic phosphoric acid auxiliary ligands, and the glass transition temperature of the hole transport material of phosphorescence device is not lower than 85° C. Because a hole transport material with high vitrification temperature is used, the device provided by the invention can overcome the instability of the device and the adverse effect on the service life of the device when the glass transition temperature of the working device when the ambient temperature is above 30-40° C. and the working device temperature is close to that of the hole transport material. Compared with the devices based on FIrpic and TAPC, the phosphorescence device provided by the invention not only has higher device efficiency, but also has better high temperature stability.

Abstract: A non-volatile memory including memory cells is provided. Each of the memory cells includes a substrate, a floating gate structure, a select gate structure, and a first doped region. The floating gate structure is disposed on the substrate. The select gate structure is disposed on the substrate and located at one side of the floating gate structure. The first doped region is disposed in the substrate at another side of the floating gate structure. The first doped regions between two adjacent memory cells are adjacent to one another and separated from one another.