Patents by Inventor Da-Jun Lin
Da-Jun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230326991Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a channel layer, a gate element on the channel layer, and source/drain elements at least partly embedded in the channel layer. The source/drain elements are on opposite sides of the gate element. The source/drain elements include a metal element and a lower silicide element between the metal element and the channel layer. The lower silicide element has a hydrogen content less than 2 at %.Type: ApplicationFiled: June 27, 2022Publication date: October 12, 2023Inventors: Da-Jun LIN, Chih-Tung YEH, Fu-Yu TSAI, Bin-Siang TSAI
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Publication number: 20230301210Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.Type: ApplicationFiled: May 26, 2023Publication date: September 21, 2023Applicant: United Microelectronics Corp.Inventors: Chich-Neng Chang, Da-Jun Lin, Shih-Wei Su, Fu-Yu Tsai, Bin-Siang Tsai
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Patent number: 11762293Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.Type: GrantFiled: May 11, 2021Date of Patent: September 19, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hao-Hsuan Chang, Da-Jun Lin, Yao-Hsien Chung, Ting-An Chien, Bin-Siang Tsai, Chih-Wei Chang, Shih-Wei Su, Hsu Ting, Sung-Yuan Tsai
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Publication number: 20230260937Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.Type: ApplicationFiled: April 25, 2023Publication date: August 17, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai
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Patent number: 11723287Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.Type: GrantFiled: September 29, 2022Date of Patent: August 8, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Shih-Wei Su, Bin-Siang Tsai, Ting-An Chien
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Patent number: 11723215Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.Type: GrantFiled: November 30, 2020Date of Patent: August 8, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Yi-An Shih, Bin-Siang Tsai, Fu-Yu Tsai
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Patent number: 11707003Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.Type: GrantFiled: January 4, 2021Date of Patent: July 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chich-Neng Chang, Da-Jun Lin, Shih-Wei Su, Fu-Yu Tsai, Bin-Siang Tsai
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Patent number: 11688790Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.Type: GrantFiled: January 6, 2021Date of Patent: June 27, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Da-Jun Lin, Ting-An Chien, Bin-Siang Tsai
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Patent number: 11676920Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.Type: GrantFiled: January 26, 2021Date of Patent: June 13, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai
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Publication number: 20230157180Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a first inter-metal dielectric (IMD) layer on the MTJ, removing part of the first IMD layer to form a damaged layer on the MTJ and a trench exposing the damaged layer, performing a ultraviolet (UV) curing process on the damaged layer, and then conducting a planarizing process to remove the damaged layer and part of the first IMD layer.Type: ApplicationFiled: December 12, 2021Publication date: May 18, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tai-Cheng Hou, Chau-Chung Hou, Da-Jun Lin, Wei-Xin Gao, Fu-Yu Tsai, Bin-Siang Tsai
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Publication number: 20230145175Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed on the gate.Type: ApplicationFiled: January 3, 2023Publication date: May 11, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Da-Jun Lin, Ting-An Chien, Bin-Siang Tsai
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Patent number: 11632889Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.Type: GrantFiled: July 14, 2021Date of Patent: April 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Bin-Siang Tsai, Ya-Jyuan Hung, Chin-Chia Yang, Ting-An Chien
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Patent number: 11605777Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile stress pieces.Type: GrantFiled: August 31, 2020Date of Patent: March 14, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Min-Hua Tsai, Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai
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Publication number: 20230047601Abstract: An infrared thermopile sensor includes a silicon cover having an infrared lens, an infrared sensing chip having duo-thermopile sensing elements, and a microcontroller chip calculating a temperature of an object. The components are in a stacked 3D package to decrease the size of the infrared thermopile sensor. The infrared sensing chip and the microcontroller chip have metal layers to shield the thermal radiation. The conversion from wrist temperature to body core temperature uses detected ambient temperature and fixed humidity or imported humidity level to calculate the body core temperature based on experimental data and curve fitting. The skin temperature compensation can be set differently for different sex gender, different standard deviation of wrist temperature and external relative humidity reading.Type: ApplicationFiled: August 16, 2021Publication date: February 16, 2023Inventors: Chein-Hsun WANG, Da-Jun LIN, Chun-Chiang CHEN, Chih-Yung TSAI, Yu-Chih LIANG, Ming LE, Chen-Tang HUANG, Tung-Yang LEE, Jenping KU
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Publication number: 20230017965Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.Type: ApplicationFiled: September 29, 2022Publication date: January 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Shih-Wei Su, Bin-Siang Tsai, Ting-An Chien
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Publication number: 20220406994Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a dielectric layer, a plurality of MTJ stacked elements and at least one dummy MTJ stacked element located in the dielectric layer, a first nitride layer covering at least the sidewalls of the MTJ stacked elements and the dummy MTJ stacked elements, a second nitride layer covering the top surfaces of the dummy MTJ stacked elements, the thickness of the second nitride layer is greater than the thickness of the first nitride layer, and a plurality of contact structures located in the dielectric layer and electrically connected with each MTJ stacked element.Type: ApplicationFiled: July 15, 2021Publication date: December 22, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Ching-Hua Hsu, Fu-Yu Tsai, Bin-Siang Tsai
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Publication number: 20220392850Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.Type: ApplicationFiled: July 7, 2021Publication date: December 8, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Chin-Chia Yang, Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai
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Patent number: 11521895Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. The air gap has a cross-section of substantially bottle shape with a flat top. A porous dielectric layer is disposed over the substrate, sealing the flat top of the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.Type: GrantFiled: May 19, 2021Date of Patent: December 6, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Bin-Siang Tsai, Chich-Neng Chang
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Publication number: 20220365433Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.Type: ApplicationFiled: May 11, 2021Publication date: November 17, 2022Inventors: Hao-Hsuan Chang, Da-Jun Lin, Yao-Hsien Chung, Ting-An Chien, Bin-Siang Tsai, Chih-Wei Chang, Shih-Wei Su, Hsu Ting, Sung-Yuan Tsai
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Patent number: 11495737Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.Type: GrantFiled: June 29, 2020Date of Patent: November 8, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Shih-Wei Su, Bin-Siang Tsai, Ting-An Chien