Abstract: Protecting a gate dielectric is achieved with a gate dielectric protection circuit coupled to a transistor at risk. The protection circuit is activated to reduce the voltage across the gate dielectric (VDIFF) to below its breakdown voltage (VBD). The protection circuit is activated when an ESD event is detected. The protection circuit provides a protection or ESD bias to reduce VDIFF below VBD.

Abstract: An RC-based electrostatic discharge protection device provides an extended snapback trigger voltage range, thereby avoiding latch-up. Two parallel current discharge paths are provided between supply terminals during an electrostatic discharge event by virtue of an added external resistor. The first current discharge path includes body resistance of the protection device and the second current discharge path includes the external resistor.

Abstract: An ESD module is presented. The ESD module includes an ESD circuit and a latch-up (LU) control circuit. The ESD circuit has a pad terminal and a low power source terminal. The LU control circuit includes a first LU terminal coupled to a high power source and an LU output terminal coupled to the ESD circuit. The ESD module has first and second operating modes. In the first operating mode, the LU control circuit is deactivated and the ESD circuit has a first triggering current It1 which is less than 100 mA. In the second operating mode, the LU control circuit is activated and the ESD circuit has a second triggering current It2 which is greater than 100 mA.

Abstract: An ESD circuit is disclosed. The ESD circuit includes a pad and a ground and a sensing element coupled between the pad and ground for sensing an ESD current. The sensing element generates an active sense output signal when an ESD current is sensed and an inactive sense output signal when no ESD current is sensed. The ESD circuit also includes a bypass element comprising a bi-polar junction transistor. The bypass element is coupled in parallel to the sensing element between the pad and ground. The active sense output signal causes the bypass element to be activated to provide a current path between the pad and ground.

Abstract: A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.

Abstract: A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals.

Abstract: A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well which encompasses the device region and a second device well disposed within the first device well. The device further includes a drift well which encompasses the second diffusion region of which edges of the drift well do not extend below the gate and is away from a channel region, and a drain well which is disposed under the second diffusion region and extends below the gate.

Abstract: A device having an ESD module is disclosed. The ESD module includes an ESD circuit coupled between first and second rails and a control circuit coupled between the rails and to the ESD circuit. When the control circuit senses an ESD event, it causes the ESD circuit to create a current path between the rails to dissipate ESD current. When no ESD event is sensed, the control circuit ensures that no current path is created between the rails to prevent latch-up.

Abstract: A device which includes a substrate defined with a device region having an ESD protection circuit is disclosed. The ESD protection circuit has a transistor. The transistor includes a gate having first and second sides. A first diffusion region is disposed adjacent to the first side of the gate and a second diffusion region is disposed in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. A drift isolation region is disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. A drain well having dopants of the first polarity type is disposed under the second diffusion region and within the first device well.

Abstract: A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.

Abstract: A cross-domain ESD protection scheme is disclosed. Embodiments include coupling a first power clamp to a first power rail and a first ground rail; providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a second ground rail; providing a first PMOS transistor having a second source, a second drain, and a second gate; coupling the second source to the first power rail; and providing, via the first power clamp, a signal to turn on the first NMOS transistor during an ESD event that occurs at the first power rail.

Abstract: A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well.

Abstract: A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region disposed adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well encompasses the device region and a second device well disposed within the first device well. The second device well encompasses the first diffusion region and at least a part of the gate. The device also includes a third well which is disposed within the second device well and a drain well which encompasses the second diffusion region and extends below the gate.

Abstract: An acceptable voltage margin between a voltage level for triggering electrostatic current discharge and a voltage level for programming operation of an OTP device is determined. Activation of an ESD protection circuit is controlled in part in response to a false trigger prevention circuit. To avoid gate oxide breakdown that may occur with a MOSFET protection device used for higher voltage requirements of an OTP device, the ESD protection circuit employs a bipolar transistor.

Abstract: A latch-up prevention structure and method for ultra-small high voltage tolerant cell is provided. In one embodiment, the integrated circuit includes an input and/or output pad, a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and also connected to a first voltage supply, a low-voltage n-well (LVNW) connected to a second voltage supply through a N+ in the LVNW, a HVNW control circuit, and a guard-ring HVNW, where the first voltage supply has higher voltage level than the second voltage supply, guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between a P+ in HVNW and N+ in LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level. The guard-ring HVNW's voltage level is matched by the floating HVNW's voltage level.

Abstract: An electrostatic discharge (ESD) protection circuit includes a clamp transistor, and inverter, a resistance-capacitance (RC) circuit, and a current mirror. The clamp transistor is coupled between a first supply node and a second supply node. The inverter has an input end and an output end, and the output end of the inverter is coupled with a gate of the clamp transistor. The RC circuit is coupled to the first supply node. The current mirror includes a first transistor and a second transistor. The first transistor is coupled between the input end of the inverter and the second supply node, and the second transistor is coupled between the RC circuit and the second supply node.

Abstract: An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source is coupled to a ground rail, and the first drain to an I/O pad; providing a gate driver control circuit including a second NMOS transistor having a second source, a second drain, and a second gate; and coupling the second drain to the first gate, the second source to the ground rail, wherein the gate driver control circuit provides a ground potential to the first gate during an ESD event occurring from the I/O pad to the ground rail.

Abstract: An approach for providing a latch-up robust PNP-triggered SCR-based device is disclosed. Embodiments include providing a silicon control rectifier (SCR) region; providing a PNP region having a first n-well region proximate the SCR region, a first N+ region and a first P+ region in the first n-well region, and a second P+ region between the SCR region and the first n-well region; coupling the first N+ region and the first P+ region to a power rail; and coupling the second P+ region to a ground rail.

Abstract: A ESD protection scheme is disclosed for circuits with multiple power domains. Embodiments include: coupling a first power clamp to a first power rail and a first ground rail of a first domain; coupling a second power clamp to a second power rail and a second ground rail of a second domain; providing a blocking circuit for blocking current from an ESD event; providing an I/O interface connection in the first domain for transmitting signals from the first domain to the blocking circuit; providing a core interface connection in the second domain for transmitting signals from the blocking circuit to the second domain; coupling an input connection of the blocking circuit to the I/O interface connection; and coupling an output connection of the blocking circuit to a core interface connection.

Abstract: A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals.