Patents by Inventor Da Woon JEONG
Da Woon JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10861864Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.Type: GrantFiled: November 13, 2019Date of Patent: December 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Da Woon Jeong, Jihye Kim, Joowon Park
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Publication number: 20200190501Abstract: The present invention relates to an expansin-agarase enzyme complex and a method of degrading agar by using the same. The use of the enzyme complex according to the present invention can efficiently degrade agar obtained from marine biomass, and thus can efficiently provide not only galactose or glucose necessary for ethanol production, but also useful biologically active substances, such as diose, triose, and oligosaccharides.Type: ApplicationFiled: January 2, 2018Publication date: June 18, 2020Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATIONInventors: Sung Ok HAN, Da-woon JEONG, Jeong-Eun HYEON
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Publication number: 20200091544Abstract: The present invention relates to an electrode assembly in which a plurality of electrode units are stacked to improve product stability when manufactured and a method for manufacturing the same. In addition, the present invention is provided to include a plurality of electrode units on which electrode tabs are formed and a full length-side separator member folded in a direction in which the electrode tabs are formed and a direction opposite to the direction in which the electrode tabs are formed while stacking the plurality of electrode units to be separated from each other.Type: ApplicationFiled: May 23, 2018Publication date: March 19, 2020Inventors: Yu Na Jeong, Jae Han Jung, Sung Pil Yoon, Won Pyo Chae, Da Woon Jeong, Jeong Min Kim, Young San Bae
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Publication number: 20200083242Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.Type: ApplicationFiled: November 13, 2019Publication date: March 12, 2020Inventors: Da Woon JEONG, Jihye KIM, Joowon PARK
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Publication number: 20200075101Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.Type: ApplicationFiled: October 22, 2019Publication date: March 5, 2020Inventors: Da Woon JEONG, Sung-Hun LEE, Seokjung YUN, Hyunmog PARK, JoongShik SHIN, Young-Bae YOON
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Patent number: 10483274Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.Type: GrantFiled: September 20, 2018Date of Patent: November 19, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Da Woon Jeong, Jihye Kim, Joowon Park
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Patent number: 10482964Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.Type: GrantFiled: July 20, 2018Date of Patent: November 19, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Da Woon Jeong, Sung-Hun Lee, Seokjung Yun, Hyunmog Park, JoongShik Shin, Young-Bae Yoon
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Publication number: 20190019804Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.Type: ApplicationFiled: September 20, 2018Publication date: January 17, 2019Inventors: Da Woon JEONG, Jihye KIM, Joowon PARK
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Publication number: 20180336950Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.Type: ApplicationFiled: July 20, 2018Publication date: November 22, 2018Inventors: Da Woon JEONG, Sung-Hun LEE, Seokjung YUN, Hyunmog PARK, JoongShik SHIN, Young-Bae YOON
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Patent number: 10083977Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.Type: GrantFiled: August 23, 2017Date of Patent: September 25, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Da Woon Jeong, Jihye Kim, Joowon Park
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Patent number: 10049744Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.Type: GrantFiled: December 19, 2016Date of Patent: August 14, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Da Woon Jeong, Sung-Hun Lee, Seokjung Yun, Hyunmog Park, JoongShik Shin, Young-Bae Yoon
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Publication number: 20170352674Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.Type: ApplicationFiled: August 23, 2017Publication date: December 7, 2017Inventors: Da Woon JEONG, Jihye KIM, Joowon PARK
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Patent number: 9748258Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.Type: GrantFiled: February 26, 2016Date of Patent: August 29, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Da Woon Jeong, Jihye Kim, Joowon Park
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Publication number: 20170200676Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.Type: ApplicationFiled: December 19, 2016Publication date: July 13, 2017Inventors: Da Woon JEONG, Sung-Hun LEE, Seokjung YUN, Hyunmog PARK, JoongShik SHIN, Young-Bae YOON
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Publication number: 20160293622Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.Type: ApplicationFiled: February 26, 2016Publication date: October 6, 2016Inventors: Da Woon JEONG, Jihye KIM, Joowon PARK
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Publication number: 20140020736Abstract: Disclosed is a method for producing a CIS-based thin film based on self-accelerated photoelectrochemical deposition. The method includes 1) mixing precursors of elements constituting a CIS-based compound with a solvent to prepare an electrolyte solution, 2) connecting an electrochemical cell including a working electrode, the electrolyte solution and a counter electrode to a voltage or current applying device to construct an electro-deposition circuit, 3) irradiating light onto the working electrode while at the same time applying a cathodic voltage or current to the working electrode to induce self-accelerated photoelectrochemical deposition, thereby electro-depositing a CIS-based thin film, and 4) annealing the electro-deposited CIS-based thin film under a gas atmosphere including sulfur or selenium.Type: ApplicationFiled: November 7, 2012Publication date: January 23, 2014Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Doh-Kwon LEE, Hong Gon KIM, Min Jae KO, Jin Young KIM, Da Woon JEONG, Bong Soo KIM