Abstract: Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

Abstract: Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

Abstract: A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.

Abstract: A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.