Patents by Inventor Dae-Hun Choi
Dae-Hun Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240169888Abstract: Disclosed is a display device including a display panel having a plurality of pixels, the display panel comprising a first display area having first resolution and a second display area having second resolution, the second resolution being lower than the first resolution, and a controller configured to generate display area information of each of the plurality of pixels, to blur an image that is displayed in the second display area based on the display area information, and to perform control such that the blurred image is displayed on the display panel.Type: ApplicationFiled: November 15, 2023Publication date: May 23, 2024Applicant: SILICON WORKS CO., LTD.Inventors: Dae Hee BAE, Bo Sung KIM, Jun Hun PARK, Ji Hong YUK, Sung Woo HAN, Ji Hoon CHOI
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Patent number: 11970613Abstract: Embodiments relate to a polymer film. The polymer film comprises a polymer resin selected from the group consisting of a polyamide-based resin and a polyimide-based resin and has a haze (HZ0) before autoclave treatment of 3% or less and a ?HZ24 represented by Equation 1a of 500% or less.Type: GrantFiled: June 26, 2020Date of Patent: April 30, 2024Assignee: SK MICROWORKS CO., LTD.Inventors: Jung Hee Ki, Sunhwan Kim, Sang Hun Choi, Dae Seong Oh, Han Jun Kim, Jin Woo Lee, Dong Jin Lim
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Publication number: 20240115641Abstract: Disclosed are an oral film and stick jelly containing glutathione and a milk thistle extract. Provided are an oral disintegrating film, an oral mucosal adhesive film, and a stick jelly that contain glutathione, a milk thistle extract, or the like as an active ingredient, and thus are highly efficacious in improving absorption in the oral mucosa, antioxidant activity, and anti-inflammatory activity, strengthening immunity, and enhancing liver function of humans and companion animals.Type: ApplicationFiled: February 17, 2022Publication date: April 11, 2024Applicants: ESTHER FORMULA CO., LTD., BIO360 CO., LTDInventors: Esther LYUH, Kun Se KIM, Eun Soo SUH, Byoung Hag KIM, Mi Young AN, Dae Seong CHEON, Jae Hun KIM, Young Jae PARK, Byeong Hyeon KIM, Hyo Seon CHOI
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Publication number: 20240109397Abstract: A method for controlling an electric heater of a vehicular heating, ventilation, and air conditioning (HVAC) system includes turning on the electric heater; determining whether an ambient air temperature of a vehicle is higher than or equal to a threshold ambient air temperature, and a battery temperature is lower than or equal to a threshold battery temperature; determining whether battery efficiency is lower than or equal to threshold efficiency when the ambient air temperature of the vehicle is higher than or equal to the threshold ambient air temperature, and the battery temperature is lower than or equal to the threshold battery temperature; and turning off the electric heater when the battery efficiency is lower than or equal to the threshold efficiency, wherein the electric heater is configured to receive electric energy from the battery.Type: ApplicationFiled: March 30, 2023Publication date: April 4, 2024Inventors: Dae Hyun Song, Chang Gi Ryu, Woo Jin Lee, Dong Ju Ko, Hyun Hun Choi, Chun Kyu Kwon, In Uk Ko
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Patent number: 11945744Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).Type: GrantFiled: April 14, 2023Date of Patent: April 2, 2024Assignees: SAMSUNG ENGINEERING CO., LTD., SAMSUNG ELECTRONICS CO., LTDInventors: Seok Hwan Hong, Dae Soo Park, Seung Joon Chung, Yong Xun Jin, Jae Hyung Park, Jae Hoon Choi, Jae Dong Hwang, Jong Keun Yi, Su Hyoung Cho, Kyu Won Hwang, June Yurl Hur, Je Hun Kim, Ji Won Chun
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Publication number: 20240087501Abstract: Disclosed is a display device including a display panel having a plurality of pixels, the display panel comprising a first display area having first resolution and a second display area having second resolution, the second resolution being lower than the first resolution, and a controller configured to generate display area information of each of the plurality of pixels, to blur an image that is displayed in the second display area based on the display area information, and to perform control such that the blurred image is displayed on the display panel.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Applicant: SILICON WORKS CO., LTD.Inventors: Dae Hee BAE, Bo Sung KIM, Jun Hun PARK, Ji Hong YUK, Sung Woo HAN, Ji Hoon CHOI
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Publication number: 20240066564Abstract: Proposed are a substrate processing apparatus and a substrate processing method capable of efficiently preventing contamination of a substrate and a processing space caused by a reverse flow of purge gas.Type: ApplicationFiled: March 27, 2023Publication date: February 29, 2024Applicant: SEMES CO., LTD.Inventors: Do Hyung KIM, Dae Hun KIM, Young Jin KIM, Tae Ho KANG, Young Joon HAN, Eun Hyeok CHOI, Jun Gwon LEE
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Publication number: 20230262980Abstract: Disclosed are a three-dimensional semiconductor memory device, a method of fabricating the same, and an electronic system including the same. The semiconductor memory device may include a substrate including a first region and a second region, a plurality of stacks including first and second stacks, each of which includes interlayer insulating layers and gate electrodes stacked alternately with the interlayer insulating layers on the substrate and has a stepped structure on the second region, an insulating layer on stepped structure of the first stack, a plurality of vertical channel structures provided on the first region to penetrate the first stack, and a separation structure separating the first and second stacks from each other. The insulating layer may include one or more dopants, and a dopant concentration of the insulating layer may decrease as a distance from the substrate increases.Type: ApplicationFiled: September 29, 2022Publication date: August 17, 2023Inventors: Seungjae Sim, Byung-Sun Park, Jaechul Lee, Dae-Hun Choi
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Publication number: 20230240072Abstract: A non-volatile memory device includes a substrate having a cell array region and an extension region. A mold structure includes a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate such that the mold structure has a step shape that steps downwardly in the extension region in a direction away from the cell array region. A channel structure penetrates through the mold structure in the cell array region, and a cell contact structure penetrates through the mold structure in the extension region. A portion of the cell contact structure is in contact with a portion of an uppermost one of the gate electrodes. The cell contact structure includes a first portion in contact with a side surface of the uppermost one of the gate electrodes and a second portion in contact with a top surface of the uppermost one of the gate electrodes. A width of the first portion is smaller than a width of the second portion.Type: ApplicationFiled: September 9, 2022Publication date: July 27, 2023Inventors: Dae-Hun CHOI, Jae Chul LEE, Byung-Sun PARK, Seung Jae SIM
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Patent number: 11018045Abstract: A deposition apparatus for depositing a material on a wafer, the apparatus including a lower shower head; an upper shower head disposed on the lower shower head, the upper shower head facing the lower shower head; and a support structure between the upper shower head and the lower shower head, the wafer being supportable by the support structure, wherein the upper shower head includes upper holes for providing an upper gas onto the wafer, the lower shower head includes lower holes for providing a lower gas onto the wafer, the support structure includes a ring body surrounding the wafer; a plurality of ring support shafts between the ring body and the lower shower head; and a plurality of wafer supports extending inwardly from a lower region of the ring body to support the wafer, and the plurality of wafer supports are spaced apart from one another.Type: GrantFiled: May 31, 2018Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Youn Seo, Byung Sun Park, Sung Jin Park, Ji Woon Im, Hyun Seok Lim, Byung Ho Chun, Yu Seon Kang, Hyuk Ho Kwon, Tae Yong Eom, Dae Hun Choi, Dong Hyeop Ha
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Publication number: 20190148211Abstract: A deposition apparatus for depositing a material on a wafer, the apparatus including a lower shower head; an upper shower head disposed on the lower shower head, the upper shower head facing the lower shower head; and a support structure between the upper shower head and the lower shower head, the wafer being supportable by the support structure, wherein the upper shower head includes upper holes for providing an upper gas onto the wafer, the lower shower head includes lower holes for providing a lower gas onto the wafer, the support structure includes a ring body surrounding the wafer; a plurality of ring support shafts between the ring body and the lower shower head; and a plurality of wafer supports extending inwardly from a lower region of the ring body to support the wafer, and the plurality of wafer supports are spaced apart from one another.Type: ApplicationFiled: May 31, 2018Publication date: May 16, 2019Inventors: Ji Youn SEO, Byung Sun PARK, Sung Jin PARK, Ji Woon IM, Hyun Seok LIM, Byung Ho CHUN, Yu Seon KANG, Hyuk Ho KWON, Tae Yong EOM, Dae Hun CHOI, Dong Hyeop HA
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Patent number: 9312270Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.Type: GrantFiled: January 9, 2015Date of Patent: April 12, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Tae Jang, Myoungbum Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yup Lee, Dae-Hun Choi
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Patent number: 9040378Abstract: Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.Type: GrantFiled: June 19, 2014Date of Patent: May 26, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Bo-Young Lee, Jong-Wan Choi, Dae-Hun Choi, Myoung-Bum Lee
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Publication number: 20150126007Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.Type: ApplicationFiled: January 9, 2015Publication date: May 7, 2015Inventors: Kyung-Tae Jang, Myoungbum Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yup Lee, Dae-Hun Choi
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Publication number: 20150064885Abstract: Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.Type: ApplicationFiled: June 19, 2014Publication date: March 5, 2015Inventors: Bo-Young Lee, Jong-Wan Choi, Dae-Hun Choi, Myoung-Bum Lee
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Publication number: 20120064682Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.Type: ApplicationFiled: September 12, 2011Publication date: March 15, 2012Inventors: Kyung-Tae Jang, Myoung Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yuo Lee, Dae-Hun Choi