Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).

Abstract: An embodiment semiconductor module includes a substrate, a heterogeneous thin film including a first semiconductor layer disposed on a first region of the substrate and a second semiconductor layer disposed on a second region of the substrate, a first semiconductor device disposed on the first semiconductor layer of the heterogeneous thin film, and a second semiconductor device disposed on the second semiconductor layer of the heterogeneous thin film, wherein one of the first semiconductor layer or the second semiconductor layer comprises gallium oxide (Ga2O3) and the other includes silicon (Si).

Abstract: Provided is a semiconductor device including a semiconductor substrate, a plurality of gate electrodes disposed on the upper surface portion of the semiconductor substrate and spaced apart from each other, a plurality of emitter electrodes disposed to be overlapped with each of the plurality of gate electrodes, and a collector electrode disposed on the lower surface of the semiconductor substrate.

Abstract: A method for manufacturing a semiconductor device includes forming an N- type layer on the first surface of the N+ type substrate, etching the N- type layer to form a trench, forming a sacrificial layer on an inner bottom surface of the trench, forming a first mask on an inner side of the trench, removing the sacrificial layer, and forming a P type shield region by implanting ions into an inner surface of the trench exposed by the removal of the sacrificial layer.

Abstract: A semiconductor device includes an N+ type substrate, an N? type layer disposed on a first surface of the N+ type substrate and having a trench opened to a surface opposite to the surface facing the N+ type substrate, a P type region disposed in the N? type layer and disposed on a side surface of the trench, a gate electrode disposed in the trench, and a source electrode and a drain electrode insulated from the gate electrode. The N? type layer includes a P type shield region covering a bottom surface and an edge of the trench.

Abstract: An embodiment semiconductor module includes a substrate, a heterogeneous thin film including a first semiconductor layer disposed on a first region of the substrate and a second semiconductor layer disposed on a second region of the substrate, a first semiconductor device disposed on the first semiconductor layer of the heterogeneous thin film, and a second semiconductor device disposed on the second semiconductor layer of the heterogeneous thin film, wherein one of the first semiconductor layer or the second semiconductor layer comprises gallium oxide (Ga2O3) and the other includes silicon (Si).

Abstract: Disclosed is a semiconductor module including a substrate, a first semiconductor layer positioned on the substrate, an insulator positioned in a partial region on the first semiconductor layer, a second semiconductor layer positioned on the insulator, a first semiconductor device formed on the first semiconductor layer, and a second semiconductor device formed on the second semiconductor layer, wherein one of the first semiconductor layer and the second semiconductor layer includes gallium oxide (Ga2O3) and the other includes silicon (Si).

Abstract: A Schottky barrier diode is provided. The Schottky barrier diode includes: an n+ type of substrate, an n? type of epitaxy layer disposed on a first surface of the n+ type of substrate and having a trench opened to an opposite side of a surface facing the substrate, a p type of region disposed on a side surface of the trench, a Schottky electrode disposed on the n? type of epitaxy layer and within the trench, and an ohmic electrode disposed on a second surface of the n+ type of substrate.

Abstract: A semiconductor device includes an n? type layer on a first surface of the substrate, a p type region on a part of the n? type layer, a gate on the n? type layer and the p type region, a first gate protection layer on the gate and a second gate protection layer on the first gate protection layer, a source on the second gate protection layer and the p type region, and a drain on the second surface of the substrate.

Abstract: A semiconductor device according to an exemplary embodiment of the present disclosure includes a substrate, an n? type layer, a plurality of trenches, a p type region, a p+ type region, an n+ type region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells. A unit cell among the plurality of unit cells may include a contact portion with which the source electrode and the n+ type region are in contact, a first branch part disposed above the contact portion on a plane, and a second branch part disposed below the contact portion on a plane, the plurality of trenches are separated from each other and disposed with a stripe shape on a plane.

Abstract: A Schottky barrier diode includes: an n? type layer disposed on a first surface of an n+ type silicon carbide substrate; a p+ type region and a p type region disposed on the n? type layer and separated from each other; an anode disposed on the n? type layer, the p+ type region, and the p type region; and a cathode disposed on a second surface of the n+ type silicon carbide substrate. The p type region is in plural, has a hexagonal shape on the plane, and is arranged in a matrix shape, and the n? type layer disposed between the p+ type region and the p type region has a hexagonal shape on the plane and encloses the p type region.

Abstract: A semiconductor device according to an exemplary embodiment of the present disclosure includes a substrate, an n? type layer, a plurality of trenches, a p type region, a p+ type region, an n+ type region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells. A unit cell among the plurality of unit cells may include a contact portion with which the source electrode and the n+ type region are in contact, a first branch part disposed above the contact portion on a plane, and a second branch part disposed below the contact portion on a plane, the plurality of trenches are separated from each other and disposed with a stripe shape on a plane.

Abstract: A semiconductor device may include: an n type of layer disposed on a first surface of a substrate; a p+ type of region disposed on the first surface of the substrate; a p? type of region disposed at a top portion of the n type of layer; a first electrode disposed on the p+ type of region and the p? type of region; and a second electrode disposed on a second surface of the substrate, wherein the side surface of the p+ type of region and the side surface of the n type of layer are in contact, and the thickness of the p+ type of region is the same as the thickness of the n type of layer and the thickness of the p? type of region.

Abstract: A semiconductor device is provide. The device includes a first n? type of layer, a second n? type of layer, and an n+ type of region sequentially disposed on a first surface of a substrate. A trench is disposed on a side surface of the second n? type of layer, a p type of region is disposed between the second n? type of layer and the trench, and a gate electrode is disposed on a bottom surface of the trench. A source electrode is disposed on the n+ type of region and a drain electrode is disposed on a second surface of the substrate. The second n? type of layer includes a first concentration layer, a second concentration layer, a third concentration layer, and a fourth concentration layer sequentially disposed on the first n? type of layer.

Abstract: A semiconductor device may include an n? type of layer disposed at a first surface of a substrate; a p? type of region and a p+ type of region disposed at a top portion of the n? type of layer; a first electrode disposed on the p? type of region and the p+ type of region; and a second electrode disposed at a second surface of the substrate, wherein the first electrode includes a first metal layer disposed on the p? type of region and a second metal layer disposed on the first metal layer, and the first metal layer is in continuous contact with the p? type of region.

Abstract: A semiconductor device may include: an n type of layer disposed on a first surface of a substrate; a p+ type of region disposed on the first surface of the substrate; a p? type of region disposed at a top portion of the n type of layer; a first electrode disposed on the p+ type of region and the p? type of region; and a second electrode disposed on a second surface of the substrate, wherein the side surface of the p+ type of region and the side surface of the n type of layer are in contact, and the thickness of the p+ type of region is the same as the thickness of the n type of layer and the thickness of the p? type of region.

Abstract: A semiconductor device is provide. The device includes a first n? type of layer, a second n? type of layer, and an n+ type of region sequentially disposed on a first surface of a substrate. A trench is disposed on a side surface of the second n? type of layer, a p type of region is disposed between the second n? type of layer and the trench, and a gate electrode is disposed on a bottom surface of the trench. A source electrode is disposed on the n+ type of region and a drain electrode is disposed on a second surface of the substrate. The second n? type of layer includes a first concentration layer, a second concentration layer, a third concentration layer, and a fourth concentration layer sequentially disposed on the first n? type of layer.

Abstract: A semiconductor device includes: an n+ type of silicon carbide substrate, an n? type of layer, first trenches, a p type of region, a p+ type of region, an n+ type of region, a gate electrode, a source electrode, and a drain electrode.

Abstract: A semiconductor device is provided and includes an n? type layer disposed at a substrate first surface. A trench, n type region, and p+ type region are disposed on the n? type layer. A p type region is disposed on the n type region. An n+ type region is disposed on the p type region. A gate insulating layer is disposed in the trench. A gate electrode is disposed on the gate insulating layer. A source electrode is disposed on an insulating layer disposed on the gate electrode, n+ type region, and p+ type region. A drain electrode is disposed at a substrate second surface. The n type region includes a first portion contacting the trench side surface and extending parallel to a substrate upper surface and a second portion contacting the first portion, separated from the trench side surface, and extending vertical to the substrate upper surface.