Patents by Inventor Dae-hyuk Kang
Dae-hyuk Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11983350Abstract: A display device comprises first and second pixels, a light-emitting layer, color conversion layers, and color filter layers, the light-emitting layer comprising first and second light-emitting elements in the first and second pixels, wherein the color conversion layers comprise first and second color conversion layers in the first and second pixels, the color filter layers comprise first and second color filter layers in the first and second pixels, the first and second light-emitting elements emit first light having a central wavelength range of a first wavelength, the first and second color conversion layers contain color conversion particles converting the first light into second light having a central wavelength range of a second wavelength longer than the first wavelength, the first color filter layer transmits the first light and blocks the second light, and the second color filter layer transmits the second light and blocks transmission of the first light.Type: GrantFiled: September 21, 2018Date of Patent: May 14, 2024Assignee: Samsung Display Co., Ltd.Inventors: Jong Hyuk Kang, Hyun Min Cho, Dae Hyun Kim, Hyun Deok Im
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Patent number: 11942567Abstract: Provided is a method of manufacturing a light-emitting element, the method including positioning a substrate, forming a first separation layer, which includes a first sacrificial layer, an etching control layer on the first sacrificial layer, and a second sacrificial layer on the etching control layer, on the substrate, forming at least one first light-emitting element on the first separation layer, and separating the first light-emitting element from the substrate.Type: GrantFiled: July 15, 2021Date of Patent: March 26, 2024Assignee: Samsung Display Co., Ltd.Inventors: Jung Hong Min, Dae Hyun Kim, Hyun Min Cho, Jong Hyuk Kang, Dong Uk Kim, Seung A Lee, Hyun Deok Im, Hyung Rae Cha
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Publication number: 20240097083Abstract: A light emitting device includes: a base substrate; a plurality of unit regions provided on the base substrate; a barrier disposed at a boundary of the unit regions to surround each of the unit regions; a dam disposed in each of the unit regions to be spaced apart from the barrier; a first electrode provided in each of unit light emitting regions surrounded by the dam; a second electrode disposed in each of the unit light emitting regions, the second electrode of which at least one region is provided opposite to the first electrode; and one or more LEDs provided in each of the unit light emitting regions, the one or more LEDs being electrically connected between the first electrode and the second electrode.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: Hyun Deok IM, Jong Hyuk KANG, Dae Hyun KIM, Joo Yeol LEE, Hyun Min CHO
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Publication number: 20240085786Abstract: The present invention relates to a naphthalimide sulfonate derivative, and a photoacid generator and a photoresist composition each comprising same and, more specifically, to a naphthalimide sulfonate derivative compound, and a photoacid generator and a photoresist composition each comprising same, wherein the compound has excellent absorbance for light of i-line (365 nm) wavelength, is greatly easy to prepare into a polymerizable composition due to very high solubility in an organic solvent, has good thermal stability, and shows a favorable acid generation rate.Type: ApplicationFiled: December 28, 2021Publication date: March 14, 2024Applicant: SAMYANG CORPORATIONInventors: Chun Rim OH, Dae Hyuk CHOI, Yu Na CHOI, Deuk Rak LEE, Ji Eun CHOI, Ki Tae KANG, Min Jung KIM, Won Jung LEE, Chi Wan LEE
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Patent number: 8784672Abstract: In a method of manufacturing a photomask pattern, a light-shielding layer pattern and an anti-reflective layer pattern are formed sequentially on a transparent substrate. Oxidation and nitridation processes are performed on a sidewall of the light-shielding layer pattern to form a protection layer pattern on a lateral portion of the light-shielding layer pattern.Type: GrantFiled: October 24, 2011Date of Patent: July 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Keun Oh, Dae-Hyuk Kang, Chan-Uk Jeon, Hyung-Ho Ko, Sung-Jae Han, Jung-Jin Kim
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Patent number: 8766343Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.Type: GrantFiled: January 23, 2012Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee, Woo-Gwan Shim, Ji-Hoon Cha, Im-Soo Park, Hyo-San Lee, Young-Hoo Kim, Jung-Min Oh
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Patent number: 8524569Abstract: In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.Type: GrantFiled: May 17, 2011Date of Patent: September 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Hyuk Kang, Jung-Won Lee, Bo-Un Yoon, Kun-Tack Lee
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Methods of forming a hole having a vertical profile and semiconductor devices having a vertical hole
Patent number: 8211804Abstract: In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.Type: GrantFiled: February 11, 2011Date of Patent: July 3, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-San Lee, Bo-Un Yoon, Kun-Tack Lee, Dae-Hyuk Kang, Seong-Ho Moon, So-Ra Han -
Publication number: 20120148944Abstract: In a method of manufacturing a photomask pattern, a light-shielding layer pattern and an anti-reflective layer pattern are formed sequentially on a transparent substrate. Oxidation and nitridation processes are performed on a sidewall of the light-shielding layer pattern to form a protection layer pattern on a lateral portion of the light-shielding layer pattern.Type: ApplicationFiled: October 24, 2011Publication date: June 14, 2012Inventors: Jong-Keun OH, Dae-Hyuk Kang, Chan-Uk Jeon, Hyung-Ho Ko, Sung-Jae Han, Jung-Jin Kim
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Publication number: 20120112317Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.Type: ApplicationFiled: January 23, 2012Publication date: May 10, 2012Inventors: Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee, Woo-Gwan Shim, Ji-Hoon Cha, Im-Soo Park, Hyo-San Lee, Young-Hoo Kim, Jung-Min Oh
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Publication number: 20120064680Abstract: A method of forming a capacitor structure and manufacturing a semiconductor device, the method of forming a capacitor structure including sequentially forming a first mold layer, a supporting layer, a second mold layer, an anti-bowing layer, and a third mold layer on a substrate having a conductive region thereon; partially removing the third mold layer, the anti-bowing layer, the second mold layer, the supporting layer, and the first mold layer to form a first opening exposing the conductive region; forming a lower electrode on a sidewall and bottom of the first opening, the lower electrode being electrically connected to the conductive region; further removing the third mold layer, the anti-bowing layer, and the second mold layer; partially removing the supporting layer to form a supporting layer pattern; removing the first mold layer; and sequentially forming a dielectric layer and upper electrode on the lower electrode and the supporting layer pattern.Type: ApplicationFiled: September 9, 2011Publication date: March 15, 2012Inventors: Jung-Min Oh, Bo-Un Yoon, Gyu-Wan Choi, Kun-Tack Lee, Dae-Hyuk Kang, Im-Soo Park, Dong-Seok Lee, Young-Hoo Kim
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Patent number: 8119476Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.Type: GrantFiled: October 18, 2010Date of Patent: February 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee, Woo-Gwan Shim, Ji-Hoon Cha, Im-Soo Park, Hyo-San Lee, Young-Hoo Kim, Jung-Min Oh
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Patent number: 8110499Abstract: An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.Type: GrantFiled: May 7, 2009Date of Patent: February 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Hyuk Kang, Young-Hoo Kim, Chang-Ki Hong, Kun-Tack Lee, Jae-Dong Lee, Dae-Hong Eom, Jeong-Nam Han
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Publication number: 20110306208Abstract: Methods for forming a mold for a storage electrode in a semiconductor device include forming an interlayer dielectric layer including a contact plug on a substrate. A first mold dielectric layer is formed of a first material on the interlayer dielectric layer. A second mold dielectric layer is formed of a second material on the first mold dielectric layer. The second material has a different etch selectivity than the first material. A first opening is formed that penetrates the first and second mold dielectric layers. The first opening is dry etched to define a second opening having a larger width in the first mold dielectric layer than in the second mold dielectric layer based on the different etch selectivity of the first and second mold dielectric layers to define the mold for the storage electrode.Type: ApplicationFiled: June 10, 2011Publication date: December 15, 2011Inventors: Jung-Won Lee, Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee
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Publication number: 20110306197Abstract: Method of manufacturing semiconductor device are provided including forming an insulation layer having a pad on a substrate; forming an etch stop layer on the insulation layer and the pad; forming a mold structure having at least one mold layer on the etch stop layer; forming a first supporting layer on the mold structure; etching the first supporting layer and the mold structure to form a first opening exposing the etch stop layer; forming a spacer on a sidewall of the first opening; etching the etch stop layer using the spacer as an etching mask to form a second opening, different from the first opening, exposing a first portion of the pad having a first associated area; etching the etch stop layer using the spacer as an etching mask to form a third opening exposing a second portion of the pad having a second associated area, the second associated area being larger than the first associated area; and etching the mold structure to form a fourth opening having a width larger than a width of the third opening.Type: ApplicationFiled: June 9, 2011Publication date: December 15, 2011Inventors: Young-Hoo Kim, Bo-Un Yoon, Kun-Tack Lee, Dae-Hyuk Kang, Im-Soo Park
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Publication number: 20110287625Abstract: A method of forming a pattern in a semiconductor device includes forming an etching object layer on a substrate, the etching object layer is an oxide that is substantially free of impurities. A mask is formed on the etching object layer, the mask is an oxide that includes impurities. The etching object layer is patterned using the mask as an etching mask and then the mask is removed. The mask is removed using an etchant having an etching selectivity to an oxide that is substantially free of impurities and an oxide that includes impurities during removing of the mask to limit damage to the patterned etching object layer during removal of the mask.Type: ApplicationFiled: April 4, 2011Publication date: November 24, 2011Inventors: Dae-Hyuk Kang, Kun-Tack Lee, Dae-Hong Eom, Bo-Un Yoon, Jeong-Nam Han
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Publication number: 20110281415Abstract: In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.Type: ApplicationFiled: May 17, 2011Publication date: November 17, 2011Inventors: Dae-Hyuk KANG, Jung-Won Lee, Bo-Un Yoon, Kun-Tack Lee
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METHODS OF FORMING A HOLE HAVING A VERTICAL PROFILE AND SEMICONDUCTOR DEVICES HAVING A VERTICAL HOLE
Publication number: 20110201203Abstract: In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.Type: ApplicationFiled: February 11, 2011Publication date: August 18, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-San Lee, Bo-Un Yoon, Kun-Tack Lee, Dae-Hyuk Kang, Seong-Ho Moon, So-Ra Han -
Publication number: 20110159660Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.Type: ApplicationFiled: October 18, 2010Publication date: June 30, 2011Inventors: Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee, Woo-Gwan Shim, Ji-Hoon Cha, Im-Soo Park, Hyo-San Lee, Young-Hoo Kim, Jung-Min Oh
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Patent number: 7959738Abstract: A method of removing a photoresist may include permeating supercritical carbon dioxide into the photoresist on a substrate having a conductive structure including a metal. The photoresist permeating the supercritical carbon dioxide may be easily removable. The photoresist permeating the supercritical carbon dioxide may be removed using a photoresist cleaning solution from the substrate. The photoresist cleaning solution may include an alkanolamine solution of about 8 percent by weight to about 20 percent by weight, a polar organic solution of about 25 percent by weight to about 40 percent by weight, a reducing agent of about 0.5 percent by weight to about 3 percent by weight with the remainder being water. The photoresist may be easily removed without damaging the conductive structure in a plasma process.Type: GrantFiled: November 16, 2007Date of Patent: June 14, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Hyuk Kang, Hyo-San Lee, Dong-Gyun Han, Chang-Ki Hong, Kun-Tack Lee