Patents by Inventor Dae-Wook Yang

Dae-Wook Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of connecting a shielding layer to ground through conductive vias
    Patent number: 7851893
    Abstract: A semiconductor device is made by providing a substrate having an interconnect structure, providing a plurality of semiconductor die each having a through silicon via (TSV), mounting the semiconductor die to the substrate to electrically connect the TSV to the interconnect structure, depositing an encapsulant between the semiconductor die, and forming a shielding layer over the encapsulant and semiconductor die. The shielding layer is electrically connected to the TSV which in turn electrically connects to the interconnect structure to isolate the semiconductor die from interference. The shielding layer is electrically connected to a ground potential through the TSV and interconnect structure. The semiconductor die includes solder bumps which are electrically connected to contact pads on the substrate. The substrate also includes solder bumps electrically connected to a conductive channel in the interconnect structure which is electrically connected to the TSV.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: December 14, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seung Won Kim, Dae Wook Yang
  • Integrated circuit underfill package system
    Patent number: 7741726
    Abstract: An integrated circuit underfill package system including providing a substrate having a dispense port, attaching a first integrated circuit die on the substrate, and supplying an underfill to the dispense port when the substrate and the first integrated circuit die are inverted.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: June 22, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Hyung Jun Jeon, Ki Youn Jang, Dae-Wook Yang
  • Semiconductor Device and Method of Connecting a Shielding Layer to Ground Through Conductive Vias
    Publication number: 20090302437
    Abstract: A semiconductor device is made by providing a substrate having an interconnect structure, providing a plurality of semiconductor die each having a through silicon via (TSV), mounting the semiconductor die to the substrate to electrically connect the TSV to the interconnect structure, depositing an encapsulant between the semiconductor die, and forming a shielding layer over the encapsulant and semiconductor die. The shielding layer is electrically connected to the TSV which in turn electrically connects to the interconnect structure to isolate the semiconductor die from interference. The shielding layer is electrically connected to a ground potential through the TSV and interconnect structure. The semiconductor die includes solder bumps which are electrically connected to contact pads on the substrate. The substrate also includes solder bumps electrically connected to a conductive channel in the interconnect structure which is electrically connected to the TSV.
    Type: Application
    Filed: June 10, 2008
    Publication date: December 10, 2009
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Seung Won Kim, Dae Wook Yang
  • INTEGRATED CIRCUIT UNDERFILL PACKAGE SYSTEM
    Publication number: 20090096112
    Abstract: An integrated circuit underfill package system including providing a substrate having a dispense port, attaching a first integrated circuit die on the substrate, and supplying an underfill to the dispense port when the substrate and the first integrated circuit die are inverted.
    Type: Application
    Filed: December 16, 2008
    Publication date: April 16, 2009
    Inventors: Hyung Jun Jeon, Ki Youn Jang, Dae-Wook Yang
  • Integrated circuit underfill package system
    Patent number: 7485502
    Abstract: An integrated circuit underfill package system including providing a substrate having a dispense port, attaching a first integrated circuit die on the substrate, and supplying an underfill to the dispense port when the substrate and the first integrated circuit die are inverted.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: February 3, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Hyung Jun Jeon, Ki Youn Jang, Dae-Wook Yang
  • INTEGRATED CIRCUIT UNDERFILL PACKAGE SYSTEM
    Publication number: 20070176285
    Abstract: An integrated circuit underfill package system including providing a substrate having a dispense port, attaching a first integrated circuit die on the substrate, and supplying an underfill to the dispense port when the substrate and the first integrated circuit die are inverted.
    Type: Application
    Filed: January 31, 2006
    Publication date: August 2, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Hyung Jun Jeon, Ki Youn Jang, Dae-Wook Yang