Patents by Inventor Dae-Young Choi
Dae-Young Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140264940Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.Type: ApplicationFiled: May 28, 2014Publication date: September 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hak-Kyoon BYUN, Dae-Young CHOI, Mi-Yeon KIM
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Publication number: 20140256089Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Choong-Bin YIM, Seung-Kon MOK, Jin-Woo PARK, Dae-Young CHOI, Mi-Yeon KIM
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Publication number: 20140246786Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.Type: ApplicationFiled: May 16, 2014Publication date: September 4, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Hun KIM, Jin-Woo PARK, Dae-Young CHOI, Mi-Yeon KIM, Sun-Hye LEE
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Patent number: 8759959Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.Type: GrantFiled: February 17, 2011Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-Bin Yim, Seung-Kon Mok, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim
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Patent number: 8759967Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.Type: GrantFiled: August 29, 2013Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hak-Kyoon Byun, Dae-Young Choi, Mi-Yeon Kim
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Patent number: 8754515Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.Type: GrantFiled: September 13, 2012Date of Patent: June 17, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Hun Kim, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim, Sun-Hye Lee
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Publication number: 20140084442Abstract: A semiconductor package includes a first package board, a first semiconductor chip arranged on the first package board, a heat transfer layer arranged on the first semiconductor chip, a heat spreader arranged on the heat transfer layer, and a housing having a molding part arranged on the first package board and directly surrounding side surfaces of the first semiconductor chip and a guide wall arranged on the molding part, with the guide wall spaced apart from the heat spreader and surrounding side surfaces of the heat spreader.Type: ApplicationFiled: September 6, 2013Publication date: March 27, 2014Inventors: Jung-Do Lee, Tae-Woo Kang, Dong-Han Kim, Yang-Hoon Ahn, Jang-Woo Lee, Dae-Young Choi
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Publication number: 20140061890Abstract: A semiconductor package may include a semiconductor chip mounted on a substrate, a molding part protecting the semiconductor chip and having a top surface at a substantially equal height to a top surface of the semiconductor chip, a heat exhausting part on the molding part and the semiconductor chip, and an adhesive part between the heat exhausting part and the molding part and between the heat exhausting part and the semiconductor chip. An interface between the heat exhausting part and the adhesive part has a concave-convex structure.Type: ApplicationFiled: August 29, 2013Publication date: March 6, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-Do Lee, Taewoo Kang, Donghan Kim, JongBo Shim, Yang-hoon Ahn, SeokWon Lee, Dae-young Choi
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Patent number: 8653640Abstract: A semiconductor package apparatus includes a first semiconductor package including a first semiconductor chip, a first substrate, a first terminal, and a first signal transfer medium, and a second semiconductor package including a second semiconductor chip, a second substrate, a second terminal, and a second signal transfer medium. At least one package connecting solder ball is located between the first terminal and the second terminal. A first solder ball guide member is positioned around the first terminal of the first substrate and includes a first guide surface for guiding a shape of the package connecting solder ball.Type: GrantFiled: April 5, 2012Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-hun Kim, Dae-young Choi, Yang-hoon Ahn, Sun-hye Lee
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Publication number: 20140001649Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.Type: ApplicationFiled: August 29, 2013Publication date: January 2, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hak-Kyoon Byun, Dae-Young Choi, Mi-Yeon Kim
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Publication number: 20130241044Abstract: According to example embodiments, a semiconductor package includes a first semiconductor chip is on a first substrate, a protective layer directly on the first semiconductor chip, and an encapsulant covering an upper surface of the first substrate. The encapsulant may contact side surfaces of the first semiconductor chip and the protective layer.Type: ApplicationFiled: November 5, 2012Publication date: September 19, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Ki KIM, Jung-Do LEE, Yang-Hoon AHN, Sun-Hye LEE, Dae-Young CHOI
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Patent number: 8531034Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.Type: GrantFiled: September 25, 2011Date of Patent: September 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hak-Kyoon Byun, Dae-Young Choi, Mi-Yeon Kim
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Patent number: 8525341Abstract: Provided are a printed circuit board (PCB) and a semiconductor package including the same. The PCB includes a core layer having a stacked structure including at least a first layer made of a first material that has a first coefficient of thermal expansion (CTE) and a second layer made of a second material that has a second CTE different from the first CTE, an upper wiring layer disposed on a first surface of the core layer, and a lower wiring layer disposed on a second surface of the core layer opposite the first surface.Type: GrantFiled: September 22, 2011Date of Patent: September 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Ki Kim, Dae-Young Choi, Mi-Yeon Kim
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Publication number: 20130001800Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.Type: ApplicationFiled: September 13, 2012Publication date: January 3, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Tae-Hun KIM, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim, Sun-Hye Lee
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Patent number: 8338941Abstract: A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second chip in the recessed portion, the second semiconductor chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via. A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second semiconductor chip in the recessed portion, the second chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via.Type: GrantFiled: July 14, 2010Date of Patent: December 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jinho Lee, Choongbin Yim, Jin-woo Park, Dae-young Choi, Mi-yeon Kim
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Publication number: 20120306075Abstract: A semiconductor package apparatus includes a first semiconductor package including a first semiconductor chip, a first substrate, a first terminal, and a first signal transfer medium, and a second semiconductor package including a second semiconductor chip, a second substrate, a second terminal, and a second signal transfer medium. At least one package connecting solder ball is located between the first terminal and the second terminal. A first solder ball guide member is positioned around the first terminal of the first substrate and includes a first guide surface for guiding a shape of the package connecting solder ball.Type: ApplicationFiled: April 5, 2012Publication date: December 6, 2012Inventors: TAE-HUN KIM, Dae-young Choi, Yang-hoon Ahn, Sun-hye Lee
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Patent number: 8293580Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.Type: GrantFiled: February 15, 2011Date of Patent: October 23, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Hun Kim, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim, Sun-Hye Lee
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Publication number: 20120193783Abstract: A package on package is provided herein, the package on package including a first semiconductor package including a first substrate, a first semiconductor chip stacked on the first substrate, a plurality of first connection members on an upper surface of the first substrate and in a first molding material, and a plurality of via holes which respectively expose the plurality of first connection members through the first molding material; a second semiconductor package including a second substrate, a second semiconductor chip stacked on the second substrate, and a plurality of second connection members on a lower surface of the second substrate; and a plurality of connection portions including a plurality of cores and a plurality of conductive fusion layers surrounding the plurality of cores, wherein the plurality of conductive fusion layers contact the upper surface of the first substrate and the lower surface of the second substrate.Type: ApplicationFiled: December 30, 2011Publication date: August 2, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Sun HONG, Dae-Young CHOI, Mi-Yeon KIM
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Publication number: 20120168917Abstract: A stack type semiconductor package and a method of fabricating the stack type semiconductor package. The stack type semiconductor package includes: a lower semiconductor package including a circuit board, a semiconductor chip which is disposed on an upper surface of the circuit board, via-pads which are arrayed on the upper surface of the circuit board around the semiconductor chip, and an encapsulation layer which encapsulates the upper surface of the circuit board and has via-holes through which the via-pads are exposed; and an upper semiconductor package which is stacked on the encapsulation layer, is electrically connected to the lower semiconductor package, and comprises internal connection terminals which are formed on a lower surface of the upper semiconductor package.Type: ApplicationFiled: October 24, 2011Publication date: July 5, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Choong-bin YIM, Dae-Young CHOI, Mi-Yeon KIM, Ji-yong PARK
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Publication number: 20120153499Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.Type: ApplicationFiled: September 25, 2011Publication date: June 21, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hak-Kyoon BYUN, Dae-Young CHOI, Mi-Yeon KIM