Patents by Inventor Daeik Daniel KIM

Daeik Daniel KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10154591
    Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: December 11, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, David Francis Berdy, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, Jonghae Kim
  • Patent number: 10141353
    Abstract: The present disclosure provides integrated circuit apparatuses and methods for manufacturing integrated circuit apparatuses. An integrated circuit apparatus may include a first insulator, the first insulator being substantially planar and having a first top surface and a first bottom surface opposite the first top surface, a first conductor disposed on the first insulator, a second insulator, the second insulator being substantially planar and having a second top surface and a second bottom surface opposite the second top surface, a second conductor disposed on the second insulator, and a dielectric layer disposed between the first bottom conductor of the first insulator and the second top conductor of the second insulator.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Daeik Daniel Kim, Jonghae Kim, Mario Francisco Velez, Chengjie Zuo, David Francis Berdy
  • Publication number: 20180315540
    Abstract: A laminate substrate inductor reduces insertion loss and improves isolation while reducing the area for integrating the laminate substrate inductor. The laminate substrate includes a spiral trace. The laminate substrate also includes a first capture pad at a first end of the spiral trace. The first end is located at a corner of the spiral trace. The first capture pad is substantially within a bounding box of the spiral trace. At least a portion of the first capture pad and an outer edge of the spiral trace have a same distance from a ground.
    Type: Application
    Filed: December 28, 2017
    Publication date: November 1, 2018
    Inventors: Daeik Daniel KIM, Babak NEJATI, Husnu Ahmet MASARACIOGLU
  • Publication number: 20180316319
    Abstract: In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 1, 2018
    Inventors: Daeik Daniel KIM, Shu ZHANG, Bonhoon KOO, Manuel ALDRETE, Jie FU, Chin-Kwan KIM, Babak NEJATI, Husnu Ahmet MASARACIOGLU
  • Patent number: 10103116
    Abstract: A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive substrate and surrounded by a first passivation layer opening. The conductive bump assembly may further include a second passivation layer opening on the passive substrate. The second passivation layer opening may be merged with the first passivation layer opening surrounding the conductive bump pad proximate an edge of the passive substrate. The conductive bump assembly may also include a conductive bump on the conductive bump pad.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: October 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Mario Francisco Velez, Changhan Hobie Yun, Chengjie Zuo, David Francis Berdy, Jonghae Kim, Niranjan Sunil Mudakatte
  • Patent number: 10103703
    Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: October 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, David Francis Berdy, Chengjie Zuo, Daeik Daniel Kim, Jonghae Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Robert Paul Mikulka
  • Patent number: 10074625
    Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.
    Type: Grant
    Filed: September 20, 2015
    Date of Patent: September 11, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Mario Francisco Velez, David Francis Berdy, Changhan Hobie Yun, Jonghae Kim, Chengjie Zuo, Daeik Daniel Kim, Je-Hsiung Jeffrey Lan, Niranjan Sunil Mudakatte, Robert Paul Mikulka
  • Patent number: 10069474
    Abstract: A device includes an acoustic resonator embedded within an encapsulating structure that at least partially encapsulates the acoustic resonator. The device includes an inductor electrically connected to the acoustic resonator. At least a portion of the inductor is embedded in the encapsulating structure.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: September 4, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Chengjie Zuo, Daeik Daniel Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Je-Hsiung Jeffrey Lan, David Francis Berdy, Yunfei Ma, Robert Paul Mikulka, Jonghae Kim
  • Patent number: 10049815
    Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 14, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Jonghae Kim, Chengjie Zuo, Mario Francisco Velez, Changhan Hobie Yun
  • Patent number: 10051741
    Abstract: An embedded layered inductor is provided that includes a first inductor layer and a second inductor layer coupled to the first inductor layer. The first inductor layer comprises a patterned metal layer that may also be patterned to form pads. The second inductor layer comprises metal deposited in a dielectric layer adjacent the patterned metal layer.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 14, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Young Kyu Song, Daeik Daniel Kim, Xiaonan Zhang, Ryan David Lane, Jonghae Kim
  • Publication number: 20180228016
    Abstract: In a package such as a radio frequency (RF) module, an external shield may be provided to shield the package from external influences as well as to shield the devices within the package from undesirable affecting devices outside of the package. The package may also include an internal shield to suppress adverse effects of the signal generated by an aggressor device within the external shield to other devices within the external shield.
    Type: Application
    Filed: February 9, 2017
    Publication date: August 9, 2018
    Inventors: Daeik Daniel KIM, Jie FU, Manuel ALDRETE, Babak NEJATI, Husnu Ahmet MASARACIOGLU
  • Patent number: 10026546
    Abstract: An apparatus includes a substrate and a three-dimensional (3D) wirewound inductor integrated within the substrate. The apparatus further includes a capacitor coupled to the 3D wirewound inductor.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: July 17, 2018
    Assignee: QUALCOMM Incorported
    Inventors: Changhan Hobie Yun, Chengjie Zuo, Daeik Daniel Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Jonghae Kim, David Francis Berdy
  • Publication number: 20180177052
    Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Inventors: Chengjie Zuo, David Francis Berdy, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, Jonghae Kim
  • Publication number: 20180145062
    Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 24, 2018
    Inventors: Je-Hsiung Jeffrey Lan, Niranjan Sunil Mudakatte, Changhan Hobie Yun, Daeik Daniel Kim, Chengjie Zuo, David Francis Berdy, Mario Francisco Velez, Jonghae Kim
  • Patent number: 9966426
    Abstract: An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 8, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Niranjan Sunil Mudakatte, Daeik Daniel Kim, David Francis Berdy, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Chengjie Zuo, Mario Francisco Velez, Robert Paul Mikulka, Jonghae Kim
  • Patent number: 9959964
    Abstract: A thin film magnet (TFM) three-dimensional (3D) inductor structure may include a substrate with conductive vias extending through the substrate. The TFM 3D inductor structure may also include a magnetic thin film layer on at least sidewalls of the conductive vias and on a first side and an opposing second side of the substrate. The TFM 3D inductor structure may further include a first conductive trace directly on the magnetic thin film layer on the first side of the substrate and electrically coupling to at least one of the conductive vias. The TFM 3D inductor structure also includes a second conductive trace directly on the magnetic thin film layer on the second side of the substrate and coupled to at least one of the conductive vias.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: May 1, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, David Francis Berdy, Daeik Daniel Kim, Chengjie Zuo, Jonghae Kim, Je-Hsiung Jeffrey Lan, Mario Francisco Velez, Niranjan Sunil Mudakatte
  • Patent number: 9954267
    Abstract: A multiplexer structure includes a passive substrate. The multiplexer structure may also include a high band filter on the passive substrate. The high band filter may include a 2D planar spiral inductor(s) on the passive substrate. The multiplexer structure may further include a low band filter on the passive substrate. The low band filter may include a 3D through-substrate inductor and a first capacitor(s) on the passive substrate. The multiplexer structure may also include a through substrate via(s) coupling the high band filter and the low band filter.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: April 24, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Daeik Daniel Kim, Mario Francisco Velez, Chengjie Zuo, David Francis Berdy, Jonghae Kim
  • Patent number: 9930783
    Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: March 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, David Francis Berdy, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, Jonghae Kim
  • Patent number: 9906318
    Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: February 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Daeik Daniel Kim, David Francis Berdy, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka, Mario Francisco Velez, Jonghae Kim, Matthew Michael Nowak, Ryan Scott C. Spring, Xiangdong Zhang
  • Publication number: 20180047687
    Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.
    Type: Application
    Filed: August 10, 2016
    Publication date: February 15, 2018
    Inventors: Daeik Daniel KIM, Jie FU, Manuel ALDRETE, Jonghae KIM, Changhan Hobie YUN, David Francis BERDY, Chengjie ZUO, Mario Francisco VELEZ