Abstract: A display apparatus includes a liquid crystal panel disposed on a back-light unit; and a viewing angle control unit disposed between the back-light unit and the liquid crystal panel, wherein the viewing angle control unit includes light-blocking patterns having a light-blocking material and variable patterns disposed between a first control electrode and a second control electrode, wherein the variable patterns are extended in a direction perpendicular to the light-blocking patterns, and wherein transmittance of each variable pattern is changed according to a voltage applied to the first control electrode and the second control electrode, thereby preventing a distraction of people around a user by selectively sharing a realized image.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: A computing system includes an ISA identifier to identify an ISA (Instruction Set Architecture) of a task; a core selector to select a core having a highest power-performance efficiency among a plurality of cores based on the identified ISA; and a task allocator to allocate the task to the selected core.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: There is provided a method of operating a computing device including a processing component based on power consumption. The method includes: obtaining power mode information about the processing component, measuring a temperature of the processing component and a current that flows through the processing component in response to the obtaining the power mode information, generating leakage power information based on the power mode information and the measured temperature and current, and storing the generated leakage power information in a memory.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: A computing system includes an ISA identifier to identify an ISA (Instruction Set Architecture) of a task; a core selector to select a core having a highest power-performance efficiency among a plurality of cores based on the identified ISA; and a task allocator to allocate the task to the selected core.

Abstract: An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.

Abstract: There is provided a method of operating a computing device including a processing component based on power consumption. The method includes: obtaining power mode information about the processing component, measuring a temperature of the processing component and a current that flows through the processing component in response to the obtaining the power mode information, generating leakage power information based on the power mode information and the measured temperature and current, and storing the generated leakage power information in a memory.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.