Abstract: Systems and methods are described for combining a plurality of memory sections with a controller, all in a single semiconductor chip. A data processing chip has two or more DRAM memory sections with at least one section being divided into a number of arrays. Data is stored in a particular memory section depending on its associated task. For instance, pixel data is stored in a frame buffer memory section, whereas data relating to pattern, cursor, and video line buffers are stored in an auxiliary memory section. These two separate sections of memory have their own set of address, read/write, activate, control and data lines. Hence, they can be accessed independently by the memory controller. Furthermore, a memory section can be subdivided into a number of distinct arrays. For the subdivided memory section, two separate and distinct address/control buses are implemented to access these arrays. The first address bus is used to specify which selected row within one of these arrays is to be activated.