Patents by Inventor Dai-Goun Kim

Dai-Goun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of planarizing non-volatile memory device
    Patent number: 6649471
    Abstract: Disclosed is a method of planarizing a non-volatile memory device. After forming a floating gate structure on a cell area of a semiconductor substrate, a conductive layer, a hard mask layer and a first insulating layer are sequentially formed on the entire surface of the resultant structure. After removing the first insulating layer of the cell area to leave a first insulating layer pattern only on the peripheral circuit area, the hard mask layer of the cell area is removed. A second insulating layer is formed on the conductive layer and the insulating layer pattern to increase the height of the insulating layer on the peripheral circuit area. The second insulating layer and the first insulating layer pattern are removed until the floating gate structure is exposed, thereby planarizing the cell area and the peripheral circuit area.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: November 18, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Soo Cho, Dong-Jun Kim, Eui-Youl Ryu, Dai-Goun Kim, Young-Hee Kim, Sang-Rok Hah, Kwang-Bok Kim, Jeong-Lim Nam, Kyung-Hyun Kim
  • Method of planarizing non-volatile memory device
    Publication number: 20030022442
    Abstract: Disclosed is a method of planarizing a non-volatile memory device. After forming a floating gate structure on a cell area of a semiconductor substrate, a conductive layer, a hard mask layer and a first insulating layer are sequentially formed on the entire surface of the resultant structure. After removing the first insulating layer of the cell area to leave a first insulating layer pattern only on the peripheral circuit area, the hard mask layer of the cell area is removed. A second insulating layer is formed on the conductive layer and the insulating layer pattern to increase the height of the insulating layer on the peripheral circuit area. The second insulating layer and the first insulating layer pattern are removed until the floating gate structure is exposed, thereby planarizing the cell area and the peripheral circuit area.
    Type: Application
    Filed: July 25, 2002
    Publication date: January 30, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min-Soo Cho, Dong-Jun Kim, Eui-Youl Ryu, Dai-Goun Kim, Young-Hee Kim, Sang-Rok Hah, Kwang-Bok Kim, Jeong-Lim Nam, Kyung-Hyun Kim