Patents by Inventor Dai Hong Kim

Dai Hong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11107681
    Abstract: A method of fabricating a semiconductor device and a semiconductor processing apparatus are provided. The method of fabricating a semiconductor device comprises preparing a semiconductor substrate having a front side and a back side, opposing each other, and forming a material layer on the semiconductor substrate. The material layer is formed on at least a portion of the back side of the semiconductor substrate while being formed on the front side of the semiconductor substrate. The material layer formed on the at least a portion of the back side of the semiconductor substrate is removed, while the material layer formed on the front side of the semiconductor substrate remains. A semiconductor process is performed to fabricate the semiconductor device using the material layer remaining on the front side of the semiconductor substrate.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Youn Seo, Ji Woon Im, Dai Hong Kim, Ik Soo Kim, Sang Ho Rha
  • Patent number: 10950544
    Abstract: A semiconductor device includes a gate pattern disposed over a lower structure, and including a gate electrode region and a gate pad region extending from the gate electrode region; and a vertical channel semiconductor layer having a side surface facing the gate electrode region of the gate pattern. The gate pad region includes a first pad region having a thickness greater than a thickness of the gate electrode region. The first pad region includes an upper surface, a lower surface opposing the upper surface, and an outer side surface. The outer side surface has a lower outer side surface and an upper outer side surface, divided from each other by a boundary portion. The lower outer side surface extends from the lower surface, and a connection portion of the lower outer side surface and the lower surface has a rounded shape.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Ik Lee, Dai Hong Kim, Ji Woon Im, Se Mee Jang, Bo Ra Nam
  • Publication number: 20200211847
    Abstract: A method of fabricating a semiconductor device and a semiconductor processing apparatus are provided. The method of fabricating a semiconductor device comprises preparing a semiconductor substrate having a front side and a back side, opposing each other, and forming a material layer on the semiconductor substrate. The material layer is formed on at least a portion of the back side of the semiconductor substrate while being formed on the front side of the semiconductor substrate. The material layer formed on the at least a portion of the back side of the semiconductor substrate is removed, while the material layer formed on the front side of the semiconductor substrate remains. A semiconductor process is performed to fabricate the semiconductor device using the material layer remaining on the front side of the semiconductor substrate.
    Type: Application
    Filed: September 20, 2019
    Publication date: July 2, 2020
    Inventors: Ji Youn SEO, Ji Woon IM, Dai Hong KIM, Ik Soo KIM, Sang Ho RHA
  • Publication number: 20200091071
    Abstract: A semiconductor device includes a gate pattern disposed over a lower structure, and including a gate electrode region and a gate pad region extending from the gate electrode region; and a vertical channel semiconductor layer having a side surface facing the gate electrode region of the gate pattern. The gate pad region includes a first pad region having a thickness greater than a thickness of the gate electrode region. The first pad region includes an upper surface, a lower surface opposing the upper surface, and an outer side surface. The outer side surface has a lower outer side surface and an upper outer side surface, divided from each other by a boundary portion. The lower outer side surface extends from the lower surface, and a connection portion of the lower outer side surface and the lower surface has a rounded shape.
    Type: Application
    Filed: June 18, 2019
    Publication date: March 19, 2020
    Inventors: DONG IK LEE, DAI HONG KIM, JI WOON IM, SE MEE JANG, BO RA NAM
  • Patent number: 10008410
    Abstract: A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Chul Park, Ji Woon Im, Dai Hong Kim, Il Woo Kim, Hyun Seok Lim
  • Publication number: 20180114722
    Abstract: A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.
    Type: Application
    Filed: March 21, 2017
    Publication date: April 26, 2018
    Inventors: Kwang Chul PARK, Ji Woon Im, Dai Hong Kim, ll Woo Kim, Hyun Seok Lim