Patents by Inventor Dai Iwata
Dai Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147730Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.Type: ApplicationFiled: November 2, 2023Publication date: May 2, 2024Inventors: Kiyokazu SHISHIDO, Kazutaka YOSHIZAWA, Dai IWATA, Hokuto KODATE
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Publication number: 20240063278Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Inventors: Dai IWATA, Hokuto KODATE
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Patent number: 11837601Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.Type: GrantFiled: May 10, 2021Date of Patent: December 5, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Jun Akaiwa, Dai Iwata, Hiroshi Nakatsuji, Eiichi Fujikura, Hiroyuki Ogawa
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Patent number: 11626397Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.Type: GrantFiled: August 28, 2020Date of Patent: April 11, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Hokuto Kodate, Hiroyuki Ogawa, Dai Iwata, Mitsuhiro Togo
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Publication number: 20220367449Abstract: A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric. A trench isolation region surrounds the first and the second active regions. The first field effect transistor includes a fringe region in which the first gate electrode extends past the active region perpendicular to the source region to drain region direction and the second field effect transistor does not include the fringe region.Type: ApplicationFiled: October 14, 2021Publication date: November 17, 2022Inventors: Akihiro YUU, Dai IWATA, Hiroyuki OGAWA
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Publication number: 20220359501Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.Type: ApplicationFiled: May 10, 2021Publication date: November 10, 2022Inventors: Jun Akaiwa, Dai Iwata, Hiroshi Nakatsuji, Eiichi Fujikura, Hiroyuki Ogawa
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Publication number: 20220359690Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.Type: ApplicationFiled: May 10, 2021Publication date: November 10, 2022Inventors: Dai IWATA, Hiroshi NAKATSUJI, Hiroyuki OGAWA, Eiichi FUJIKURA
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Patent number: 11322597Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.Type: GrantFiled: August 28, 2020Date of Patent: May 3, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Hokuto Kodate, Hiroyuki Ogawa, Dai Iwata, Mitsuhiro Togo
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Publication number: 20220069097Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Hokuto KODATE, Hiroyuki OGAWA, Dai IWATA, Mitsuhiro TOGO
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Publication number: 20220068915Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Hokuto KODATE, Hiroyuki OGAWA, Dai IWATA, Mitsuhiro TOGO
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Patent number: 10770459Abstract: A silicon oxide liner, a silicon nitride liner, and a planarization silicon oxide layer may be sequentially formed over p-type and n-type field effect transistors. A patterned dielectric material layer covers an entirety of the n-type field effect transistor and does not cover at least a fraction of each area of p-doped active regions. An anisotropic etch process is performed to form p-type active region via cavities extending to a respective top surface of the p-doped active regions and n-type active region via cavities having a respective bottom surface at, or within, one of the silicon nitride liner and the silicon oxide liner. Boron-doped epitaxial pillar structures may be formed on top surfaces of the p-type active regions employing a selective epitaxy process. The n-type active region via cavities are extended to top surfaces of the n-doped active regions. Contact via structures are formed in the via cavities.Type: GrantFiled: December 20, 2018Date of Patent: September 8, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Dai Iwata, Yasushi Ishii, Hiroshi Nakatsuji, Kiyokazu Shishido, Hiroyuki Ogawa
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Patent number: 10748919Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.Type: GrantFiled: May 25, 2018Date of Patent: August 18, 2020Assignee: SANDISK TECHNOLOGY LLCInventors: Dai Iwata, Hiroyuki Ogawa, Kazutaka Yoshizawa, Yasuaki Yonemochi
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Publication number: 20190296012Abstract: A silicon oxide liner, a silicon nitride liner, and a planarization silicon oxide layer may be sequentially formed over p-type and n-type field effect transistors. A patterned dielectric material layer covers an entirety of the n-type field effect transistor and does not cover at least a fraction of each area of p-doped active regions. An anisotropic etch process is performed to form p-type active region via cavities extending to a respective top surface of the p-doped active regions and n-type active region via cavities having a respective bottom surface at, or within, one of the silicon nitride liner and the silicon oxide liner. Boron-doped epitaxial pillar structures may be formed on top surfaces of the p-type active regions employing a selective epitaxy process. The n-type active region via cavities are extended to top surfaces of the n-doped active regions. Contact via structures are formed in the via cavities.Type: ApplicationFiled: December 20, 2018Publication date: September 26, 2019Inventors: Dai Iwata, Yasushi Ishii, Hiroshi Nakatsuji, Kiyokazu Shishido, Hiroyuki Ogawa
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Publication number: 20180277566Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.Type: ApplicationFiled: May 25, 2018Publication date: September 27, 2018Inventors: Dai Iwata, Hiroyuki Ogawa, Kazutaka Yoshizawa, Yasuaki Yonemochi
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Patent number: 9991280Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.Type: GrantFiled: February 16, 2017Date of Patent: June 5, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Tadashi Nakamura, Jin Liu, Kazuya Tokunaga, Marika Gunji-Yoneoka, Matthias Baenninger, Hiroyuki Kinoshita, Murshed Chowdhury, Jiyin Xu, Dai Iwata, Hiroyuki Ogawa, Kazutaka Yoshizawa, Yasuaki Yonemochi
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Publication number: 20170236835Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.Type: ApplicationFiled: February 16, 2017Publication date: August 17, 2017Inventors: Tadashi NAKAMURA, Jin LIU, Kazuya TOKUNAGA, Marika GUNJI-YONEOKA, Matthias BAENNINGER, Hiroyuki KINOSHITA, Murshed CHOWDHURY, Jiyin XU, Dai IWATA, Hiroyuki OGAWA, Kazutaka YOSHIZAWA, Yasuaki YONEMOCHI
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Patent number: 9613971Abstract: A NAND flash memory array includes a select line having a first edge region containing a first portion of floating gate material and a second edge region containing a second portion of floating gate material, and having a central region between the first edge region and the second edge region where no floating gate material is present.Type: GrantFiled: July 24, 2015Date of Patent: April 4, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Masahiro Yaegashi, Kota Funayama, Takeshi Kawamura, Dai Iwata
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Publication number: 20170025425Abstract: A NAND flash memory array includes a select line having a first edge region containing a first portion of floating gate material and a second edge region containing a second portion of floating gate material, and having a central region between the first edge region and the second edge region where no floating gate material is present.Type: ApplicationFiled: July 24, 2015Publication date: January 26, 2017Inventors: Masahiro Yaegashi, Kota Funayama, Takeshi Kawamura, Dai Iwata
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Patent number: 9443862Abstract: A NAND flash memory includes a select transistor having a first region formed of a stack of layers on the substrate surface, and a second region that includes an opening through an interpoly dielectric layer, floating gate layer, and tunnel dielectric layer, the opening separated from the substrate surface by a select gate dielectric on the substrate surface, the opening filled by a control gate layer.Type: GrantFiled: July 24, 2015Date of Patent: September 13, 2016Assignee: SanDisk Technologies LLCInventors: Dai Iwata, Yusuke Yoshida, Kazutaka Yoshizawa