Abstract: A clock multiplier circuit receives a clock input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be used as the clock output signal, wherein the pulses have a pulsewidth that is independent of the number of pulses generated and independent of the frequency of the clock input signal. The clock multiplier circuit includes an oscillator and a logic circuit which generates a control signal for synchronization of the pulses to the control signal and to mask the pulses after a selected number of pulses have been output as the clock output signal. The clock multiplier circuit causes a number of unmasked pulses to be output as the clock output signal in response to the control signal, while other pulses are masked.

Abstract: In one embodiment, a clock multiplier circuit is coupled to receive an input signal and is configured to generate an output clock signal. The clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal. The number of pulses is selectable. In another embodiment, the clock multiplier circuit includes a circuit and an oscillator. The circuit is configured to cause a number of pulses on the output clock signal of the clock multiplier circuit responsive to a control signal. The oscillator is configured to generate a stream pulses having the width, wherein the circuit is coupled to receive the stream of pulses.

Abstract: A clock multiplier circuit is receives an input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be used as the clock output signal, wherein the pulses have a pulsewidth that is independent of the number of pulses generated and independent of the frequency of a clock control signal used for masking. The clock multiplier circuit includes an oscillator, a storage device for synchronization of the masking signal to the pulses and a logic circuit to generate the clock output signal. The clock multiplier circuit causes a number of unmasked pulses to be output as the output clock signal in response to the clock control signal, while other pulses are masked.

Abstract: In one embodiment, a clock multiplier circuit is coupled to receive an input signal and is configured to generate an output clock signal. The clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal. The number of pulses is selectable. In another embodiment, the clock multiplier circuit includes a circuit and an oscillator. The circuit is configured to cause a number of pulses on the output clock signal of the clock multiplier circuit responsive to a control signal. The oscillator is configured to generate a stream pulses having the width, wherein the circuit is coupled to receive the stream of pulses.

Abstract: A method and apparatus for testing an electrically programmable read-only-memory which is embedded within logic or other digital circuitry on an integrated circuit is described. An integrated circuit tester is used to test the electrically programmable read-only-memory along with the logic or other digital circuitry by encoding certain test channels of the integrated circuit tester, and inputting the encoded test channels into a high voltage signal decoding circuit specially adapted to generating a high voltage, programming voltage required by the electrically programmable read-only-memory when the programming of certain test bits in the electrically programmable read-only-memory is conducted.

Abstract: A method for simulating a logic device is described wherein a sequence of input vectors to a computer simulation is reduced in order to save computational time and data storage requirements when the sequence includes a series of redundant input vectors having the same expected output vectors. The method reduces the number of redundant input vectors to be applied to the computer simulation by eliminating all but the first input vector of series while encoding a plurality of control bits associated with that input vector with information indicating the number of redundant input vectors being eliminated. Subsequently, after the simulation of the logic device, the output vectors resulting from the simulation are combined with their respective input vectors to form a set of test vectors.