Abstract: A semiconductor device includes a stacked via structure including a plurality of first vias formed over a substrate, a first interconnect formed on the plurality of first vias, a plurality of second vias formed on the first interconnect, and a second interconnect formed on the plurality of second vias. One of the first vias closest to one end part of the first interconnect and one of the second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in the plane, and the first interconnect has a first extension part extending from a position of an end of the first via toward the one end part of the first interconnect and having a length which is more than six times as long as a via width of the first via.

Abstract: A semiconductor device includes a first interconnect 31; a second interconnect 32 which is formed in a different interconnect layer from that of the first interconnect 31, and which has a wider line width than that of the first interconnect 31; and first and second plugs 51 and 52 which are formed in a region where the first and second interconnects 31 and 32 extend in the same direction so as to overlap one above the other, and which electrically connect the first and second interconnects 31 and 32. The first plug 51 has a larger base area than that of the second plug 52, and is formed on an end side of the first interconnect 31 with respect to the second plug 52.

Abstract: A semiconductor device includes a first interconnect 31; a second interconnect 32 which is formed in a different interconnect layer from that of the first interconnect 31, and which has a wider line width than that of the first interconnect 31; and first and second plugs 51 and 52 which are formed in a region where the first and second interconnects 31 and 32 extend in the same direction so as to overlap one above the other, and which electrically connect the first and second interconnects 31 and 32. The first plug 51 has a larger base area than that of the second plug 52, and is formed on an end side of the first interconnect 31 with respect to the second plug 52.

Abstract: In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes. The dummy transistors are in an OFF state all the time. The gate length of each of the dummy gate electrodes is extended over an end portion of a diffusion region toward the inside of the standard cell. Thus, the total surface area and the total perimeter of respective gate electrodes of all transistors provided in the standard cell are increased. As a result, for example, even though shapes of gate electrodes of transistors vary between the standard cell and each of other standard cells, transistor characteristics are substantially equal among the standard cells. Therefore, variations in delays of signals generated between the standard cells can be suppressed.

Abstract: In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes. The dummy transistors are in an OFF state all the time. The gate length of each of the dummy gate electrodes is extended over an end portion of a diffusion region toward the inside of the standard cell. Thus, the total surface area and the total perimeter of respective gate electrodes of all transistors provided in the standard cell are increased. As a result, for example, even though shapes of gate electrodes of transistors vary between the standard cell and each of other standard cells, transistor characteristics are substantially equal among the standard cells. Therefore, variations in delays of signals generated between the standard cells can be suppressed.