Patents by Inventor Daigo Ichinose
Daigo Ichinose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150372007Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body including a plurality of first layers and a plurality of second layers on a substrate. The method includes forming a first slit and a second slit simultaneously by dry-etching the stacked body. The first slit causes a part of the stacked body to have a comb-shaped pattern including a plurality of line parts isolated in a first direction and extending in a second direction. The second slit surrounds the comb-shaped pattern with a closed pattern. The method includes forming a hole in the line parts of the stacked body. The method includes forming a charge storage film and a semiconductor body in the hole.Type: ApplicationFiled: June 5, 2015Publication date: December 24, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Junichi HASHIMOTO, Katsunori Yahashi, Daigo Ichinose, Tadashi Iguchi
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Publication number: 20150255485Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a stack structure disposed above the substrate and including insulation layers and conductive layers stacked alternatively; and a select gate electrode layer disposed above the stack structure; holes extending through the stack structure and the electrode layer; a connecting portion connecting lower portions of adjacent holes; and a pillar insulating film and semiconductor pillars disposed in the connected holes and in the connecting portion. A back gate is disposed between a portion above the connecting portion and the stack structure. An isolation trench is disposed between the adjacent and connected pillars to isolate the stack structure and the electrode layer. The trench has a bottom portion contacting the back gate. A bottom surface of the trench is lower than an upper surface of the back gate. A metal silicide is disposed in a portion where the back gate contacts the trench.Type: ApplicationFiled: March 4, 2015Publication date: September 10, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hisashi KAMEOKA, Daigo ICHINOSE
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Publication number: 20150255486Abstract: A nonvolatile semiconductor storage device including a semiconductor substrate; a stack structure disposed above the substrate and including insulation layers and conductive layers stacked alternatively above one another; a select gate electrode layer disposed above the stack structure; at least one hole extending through the stack structure and the select gate electrode layer; at least one semiconductor pillar disposed along an inner side of the at least one hole; storage layers disposed between the at least one semiconductor pillar and the conductive layers; a gate insulating film disposed between the at least one semiconductor pillar and the select gate electrode layer; an isolation trench disposed so as to isolate the select gate electrode layer, the trench having a bottom portion being lower than an upper surface of an uppermost conductive layer; and a metal silicide disposed in a portion of the conductive layer in the uppermost layer contacting the trench.Type: ApplicationFiled: March 4, 2015Publication date: September 10, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hisashi KAMEOKA, Daigo ICHINOSE
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Patent number: 8946809Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method includes forming a first stopper film forming a lower gate layer, making a recess in the lower gate layer, filling a sacrificial film into the recess, forming a second stopper film, making an opening in the second stopper film, forming a stacked body. The stacked body includes electrode films and insulating films. The method includes, making a slit in the stacked body, making a hole in the stacked body, removing the sacrificial film via the hole, forming a memory film including a charge storage film. The method includes forming a channel body on a side wall of the memory film. An etching rate of the first stopper film and the second stopper film is lower than an etching rate of the electrode films and the insulating films.Type: GrantFiled: September 4, 2013Date of Patent: February 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhide Takamura, Ryota Katsumata, Masaru Kidoh, Yoshihiro Uozumi, Daigo Ichinose, Toru Matsuda
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Publication number: 20140284691Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method includes forming a first stopper film forming a lower gate layer, making a recess in the lower gate layer, filling a sacrificial film into the recess, forming a second stopper film, making an opening in the second stopper film, forming a stacked body. The stacked body includes electrode films and insulating films. The method includes, making a slit in the stacked body, making a hole in the stacked body, removing the sacrificial film via the hole, forming a memory film including a charge storage film. The method includes forming a channel body on a side wall of the memory film. An etching rate of the first stopper film and the second stopper film is lower than an etching rate of the electrode films and the insulating films.Type: ApplicationFiled: September 4, 2013Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhide Takamura, Ryota Katsumata, Masaru Kidoh, Yoshihiro Uozumi, Daigo Ichinose, Toru Matsuda
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Patent number: 8791524Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile semiconductor memory device. The method can includes forming a semiconductor layer containing an impurity and forming a pattern on the semiconductor layer. The method can include forming first insulating layers in a stripe shape from a surface of the semiconductor layer toward an inside and forming a first insulating film on the semiconductor layer and on the first insulating layers to form a stacked body including electrode layers on the first insulating film. The method can include forming a pair of holes in the stacked body and forming a space portion connected to a lower end of the holes. The method can include forming a memory film on a side wall of the holes. In addition, the method can include forming a channel body layer on a surface of the memory film.Type: GrantFiled: March 16, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Daigo Ichinose, Hanae Ishihara
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Patent number: 8723247Abstract: According to one embodiment, a semiconductor memory device includes a plurality of gate electrode films arranged parallel to each other along a direction, a semiconductor member extending in the direction, and passing through the plurality of gate electrode films, and a charge storage film provided between the gate electrode films and the semiconductor member. Protrusions are provided projecting along the direction at the ends of the gate electrode films in opposition to the semiconductor member. A gaseous layer is formed in a part of a gap between the gate electrode films.Type: GrantFiled: August 26, 2011Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yosuke Komori, Daigo Ichinose
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Patent number: 8692311Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include selectively implanting an impurity into a underlying layer containing silicon using a mask to form a boron-added region and an etched region. The boron-added region contains boron, and a boron concentration of the etched region is lower than a boron concentration in the boron added region. The method can include forming a pair of holes reaching the etched region in the stacked body including a plurality of layers of electrode layers. The method can include forming a depression part connected to a lower end of each of the pair of holes in the underlying layer by removing the etched region through the holes using an etching solution.Type: GrantFiled: September 20, 2011Date of Patent: April 8, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shinohara, Daigo Ichinose
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Patent number: 8436416Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a plurality of semiconductor pillars and a charge storage film. The stacked body is provided on the substrate, with a plurality of insulating films alternately stacked with a plurality of electrode films, and includes a hydrophobic layer provided between one of the insulating films and one of the electrode films. The hydrophobic layer has higher hydrophobicity than the electrode films. The plurality of semiconductor pillars extend in a stacking direction of the stacked body and pierce the stacked body, and the charge storage film is provided between the electrode films and one of the semiconductor pillars.Type: GrantFiled: July 20, 2010Date of Patent: May 7, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Daigo Ichinose, Tadashi Iguchi
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Publication number: 20130069140Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile semiconductor memory device. The method can includes forming a semiconductor layer containing an impurity and forming a pattern on the semiconductor layer. The method can include forming first insulating layers in a stripe shape from a surface of the semiconductor layer toward an inside and forming a first insulating film on the semiconductor layer and on the first insulating layers to form a stacked body including electrode layers on the first insulating film. The method can include forming a pair of holes in the stacked body and forming a space portion connected to a lower end of the holes. The method can include forming a memory film on a side wall of the holes. In addition, the method can include forming a channel body layer on a surface of the memory film.Type: ApplicationFiled: March 16, 2012Publication date: March 21, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Daigo ICHINOSE, Hanae ISHIHARA
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Publication number: 20120244673Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include selectively implanting an impurity into a underlying layer containing silicon using a mask to form a boron-added region and an etched region. The boron-added region contains boron, and a boron concentration of the etched region is lower than a boron concentration in the boron added region. The method can include forming a pair of holes reaching the etched region in the stacked body including a plurality of layers of electrode layers. The method can include forming a depression part connected to a lower end of each of the pair of holes in the underlying layer by removing the etched region through the holes using an etching solution.Type: ApplicationFiled: September 20, 2011Publication date: September 27, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi SHINOHARA, Daigo Ichinose
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Publication number: 20120211820Abstract: According to one embodiment, a semiconductor memory device includes a plurality of gate electrode films arranged parallel to each other along a direction, a semiconductor member extending in the direction, and passing through the plurality of gate electrode films, and a charge storage film provided between the gate electrode films and the semiconductor member. Protrusions are provided projecting along the direction at the ends of the gate electrode films in opposition to the semiconductor member. A gaseous layer is formed in a part of a gap between the gate electrode films.Type: ApplicationFiled: August 26, 2011Publication date: August 23, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yosuke KOMORI, Daigo ICHINOSE
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Patent number: 8062980Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a core material on a workpiece; forming a coating film comprising an amorphous material so as to cover an upper surface and side faces of the core material; crystallizing the coating film by applying heat treatment; forming a sidewall mask by removing the crystallized coating film while leaving a portion thereof located on the side faces of the core material; removing the core material after forming the sidewall mask; and etching the workpiece using the sidewall mask as a mask after removing the core material.Type: GrantFiled: March 26, 2009Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Daigo Ichinose, Tadashi Iguchi
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Patent number: 7986000Abstract: A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a seconType: GrantFiled: September 22, 2009Date of Patent: July 26, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Mizukami, Kiyohito Nishihara, Masaki Kondo, Takashi Izumida, Hirokazu Ishida, Atsushi Fukumoto, Fumiki Aiso, Daigo Ichinose, Tadashi Iguchi
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Publication number: 20110115014Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a plurality of semiconductor pillars and a charge storage film. The stacked body is provided on the substrate, with a plurality of insulating films alternately stacked with a plurality of electrode films, and includes a hydrophobic layer provided between one of the insulating films and one of the electrode films. The hydrophobic layer has higher hydrophobicity than the electrode films. The plurality of semiconductor pillars extend in a stacking direction of the stacked body and pierce the stacked body, and the charge storage film is provided between the electrode films and one of the semiconductor pillars.Type: ApplicationFiled: July 20, 2010Publication date: May 19, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daigo ICHINOSE, Tadashi Iguchi
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Publication number: 20100117135Abstract: A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a seconType: ApplicationFiled: September 22, 2009Publication date: May 13, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Makoto MIZUKAMI, Kiyohito Nishihara, Masaki Kondo, Takashi Izumida, Hirokazu Ishida, Atsushi Fukumoto, Fumiki Aiso, Daigo Ichinose, Tadashi Iguchi
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Publication number: 20090286401Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a core material on a workpiece; forming a coating film comprising an amorphous material so as to cover an upper surface and side faces of the core material; crystallizing the coating film by applying heat treatment; forming a sidewall mask by removing the crystallized coating film while leaving a portion thereof located on the side faces of the core material; removing the core material after forming the sidewall mask; and etching the workpiece using the sidewall mask as a mask after removing the core material.Type: ApplicationFiled: March 26, 2009Publication date: November 19, 2009Inventors: Daigo Ichinose, Tadashi Iguchi