Abstract: A storage battery control method includes receiving capacity information indicating chargeable and dischargeable capacities of a plurality of storage batteries; receiving use permission information indicating whether at least some of the plurality of storage batteries are available for the frequency control; determining target storage batteries to be used for the frequency control among storage batteries of the plurality of storage batteries indicated as available by the received use permission information; determining a bid capacity used for the frequency control, the bid capacity being equal to or less than a total value of the chargeable and dischargeable capacities of the target storage batteries; and submitting a bid for the frequency control under a bid condition including the bid capacity.

Abstract: A method of setting which includes: obtaining, from a smart meter, an ID of the smart meter; obtaining, from a HEMS-controller, an ID and a certificate of the HEMS-controller and an ID and a certificate of an appliance controlled by the HEMS-controller; generating management information in which the ID of the smart meter, the ID and the certificate of the HEMS-controller, and the ID and the certificate of the appliance are associated with one another; and transmitting, based on the management information, the ID and the certificate of the HEMS-controller and the ID and the certificate of the appliance which are associated with the ID of the smart meter, to the smart meter.

Abstract: A storage battery control method includes receiving capacity information indicating chargeable and dischargeable capacities of a plurality of storage batteries; receiving use permission information indicating whether at least some of the plurality of storage batteries are available for the frequency control; determining target storage batteries to be used for the frequency control among storage batteries of the plurality of storage batteries indicated as available by the received use permission information; determining a bid capacity used for the frequency control, the bid capacity being equal to or less than a total value of the chargeable and dischargeable capacities of the target storage batteries; and submitting a bid for the frequency control under a bid condition including the bid capacity.

Abstract: A power rate calculation method for used in a facility that has the plurality of privately-used areas and a common area, one or more power generators are installed in the common area, includes: obtaining a plurality of first power amounts consumed by each of the privately-used areas, detecting whether or not a second power amount generated by the one or more power generators is larger than or equal to a third power amount consumed by both of the plurality of privately-used areas and the common area; and calculating the power rates from the plurality of first power amounts by applying a first rate structure when the second power amount is larger than or equal to the third power amount and by applying a second rate structure that is different from the first rate structure when the second power amount is smaller than the third power amount.

Abstract: A method of setting which includes: obtaining, from a smart meter, an ID of the smart meter; obtaining, from a HEMS-controller, an ID and a certificate of the HEMS-controller and an ID and a certificate of an appliance controlled by the HEMS-controller; generating management information in which the ID of the smart meter, the ID and the certificate of the HEMS-controller, and the ID and the certificate of the appliance are associated with one another; and transmitting, based on the management information, the ID and the certificate of the HEMS-controller and the ID and the certificate of the appliance which are associated with the ID of the smart meter, to the smart meter.

Abstract: An encoder includes an information holding section which stores flag bytes and an initial address, a data generation section which generates sets of first parity symbols from the initial address and the flag bytes, a parity generation section which generates and outputs sets of second parity symbols, for each column of data units included in the block, from the columns of data units included in the block and input user control data. The data generation section generates the addresses and the sets of first parity symbols, required to generate the columns of data units included in the block, based on the initial address and the flag bytes, selects necessary portions from the flag bytes and the addresses and the sets of first parity symbols generated, and outputs the portions to the parity generation section, as the columns of data units included in the block.

Abstract: In an LSI that determines timing of DRAM refresh by a refresh timer to synchronize an external I/O signal and DRAM refresh timing with each other, a circuit configuration capable of controlling a value of the refresh timer by a CPU at arbitrary timing is employed. Alternatively, a circuit configuration capable of controlling the value of the refresh timer at arbitrary timing by an external terminal, or a circuit configuration capable of controlling the refresh timing directly from the external terminal without through the refresh timer.

Abstract: A data processing device of the invention has an ID creator unit (300) which adds ID information which is set by a CPU and the number of sectors, and outputs a result of the addition as ID information; a scramble SEED value table (103) which produces an initial scramble SEED value, by using the ID information which is outputted from the ID creator unit (300); a normal scramble filter (104) which produces a scramble SEED value (402) for data to be transferred; a frame jumping scramble filter (301) which holds a scramble SEED value of a jumping destination (401) in preparation for jumping; and a selector (105) which selects one of the scramble SEED value (401) and the scramble SEED value (402) and outputs the selected value to the normal scramble filter (104). Accordingly, the data processing device can perform a scrambling process and a de-scrambling process, without depending on the reliability of the data being transferred.

Abstract: An encoder includes an information holding section which stores flag bytes and an initial address, a data generation section which generates sets of first parity symbols from the initial address and the flag bytes, a parity generation section which generates and outputs sets of second parity symbols, for each column of data units included in the block, from the columns of data units included in the block and input user control data. The data generation section generates the addresses and the sets of first parity symbols, required to generate the columns of data units included in the block, based on the initial address and the flag bytes, selects necessary portions from the flag bytes and the addresses and the sets of first parity symbols generated, and outputs the portions to the parity generation section, as the columns of data units included in the block.

Abstract: The memory access method of the present invention comprises preparing upper addresses separately from the address width of the Pseudo SRAM (200) as virtual addresses at cutting out inspection patterns, and utilizing the Pseudo SRAM (200) as a test memory having the address width of the internal CPU (101). Then, while there are only actual addresses in the number which corresponds to the memory capacity, when the memory is accessed with exceeding the actual address value at the inspection, the actual address and virtual address are distinguished from each other based on the number of times of accesses. Thereby, the extension of addresses up to the number of addresses which are used in the internal CPU is performed to the maximum, and thereby the address insufficiency at using the real memory is solved.

Abstract: There is provided an optical disc device which can evaluate in a short time as to whether an optical disc is recorded with satisfying the standard or not. An optical disc device for measuring a recording deviation amount of data recorded on an optical disc on which physical addresses are previously provided, includes an address detection circuit which detects the physical address and outputs a physical address detection signal, a timer which is operated in synchronization with reproduced data from the optical disc, a recording deviation amount measurement circuit which measures the recording deviation amount of data recorded on the optical disc by using the physical address detection signal and the count value of the timer, a memory which stores the measured recording deviation amount, and a data transfer circuit which transfers the recording deviation amount to the memory.

Abstract: When performing data descrambling for data including errors, a countermeasure against an error in a seed value that is required for the descrambling is realized in a system having no CPU. There are provided an FIFO unit (202) in which data are stored, an error correction unit (205) for receiving the data contents from the FIFO unit and performing error detection, an ID holding register (204) for holding a seed that is needed for data descrambling or information that is needed for seed generation when the data contents are judged as correct data as a result of the error detection by the error correction unit, and a descrambling unit (203) for receiving the data from the FIFO and performing descrambling by using the value stored in the ID holding register. Therefore, it is possible to perform data descrambling even in a situation where a CPU cannot manage the seed value because the transfer data are used.

Abstract: A data transfer device is provided for descrambling and deinterleaving scrambled interleaved data and transferring the resultant data. An interleave memory stores interleaved data in descrambling units. A DMA device outputs data position information indicating a storage position of each byte of the interleaved data stored in the interleave memory. A descrambling device receives data read out from each column of the interleave memory 13 in units of n bytes (n is a positive integer), and descrambles the data based on the data position information output from the DMA device.

Abstract: In a data interleaving apparatus, a SRAM sorting circuit 800 judges which the first half (SRAMs 700 and 710) or the latter half (SRAMs 720 and 730) of memory region SRAMs 700 through 730 address information for deinterleaving data transmitted by a DMA apparatus 100 corresponds to, and perform allocation. The DMA apparatus 100 transmits two addresses each time and data corresponding to one of the two addresses is written in a first memory region (SRAM 700 or 720) divided in a different manner from the above, and at the same time, data corresponding to the other one of the addresses is written in a second memory region (SRAM 710 or 730). In a DMA apparatus 200 for transmitting an address for taking out interleave data, a SRAM sorting circuit 810 performs, in the same manner, simultaneous processing to the first half and latter half regions in the memory SRAMs and simultaneous processing to the first and second memory regions. Accordingly, operation speed can be improved without increasing a frequency.

Abstract: A data processing device of the invention has an ID creator unit (300) which adds ID information which is set by a CPU and the number of sectors, and outputs a result of the addition as ID information; a scramble SEED value table (103) which produces an initial scramble SEED value, by using the ID information which is outputted from the ID creator unit (300); a normal scramble filter (104) which produces a scramble SEED value (402) for data to be transferred; a frame jumping scramble filter (301) which holds a scramble SEED value of a jumping destination (401) in preparation for jumping; and a selector (105) which selects one of the scramble SEED value (401) and the scramble SEED value (402) and outputs the selected value to the normal scramble filter (104). Accordingly, the data processing device can perform a scrambling process and a de-scrambling process, without depending on the reliability of the data being transferred.

Abstract: In a case where a data missing area has occurred when a memory portion in a SYNC information set buffer memory is being overwritten with SYNC information sets (error correction data), an initialization DMA unit obtains the starting address and the end address in the data missing area from an address setting DMA device, and writes a specific value indicating that main data contains errors at each address in the data missing area between the starting address and the end address for initialization of the data missing area. Therefore, even in the case of the occurrence of the data missing area in the memory in which the error correction data indicating the presence/absence of errors in the main data is written over existing data and stored, the errors in the main data are corrected properly in accordance with data output from the memory.