Abstract: An imaging device includes a camera unit and a control unit. A first power source voltage is transferred from the control unit to the camera unit by a power source line and is input to the camera unit as a second power source voltage. The control unit measures a value of a voltage generated at a point connecting the power source line and the control unit. The voltage at the point is generated based on both the second power source voltage held in a capacitor of the camera unit and a resistance component of the power source line. The control unit calculates a resistance value of the power source line based on the measured value. The control unit adjusts a value of the first power source voltage based on the resistance value.

Abstract: A signal processing device includes: a processor including at least one or more pieces of hardware, the processor being configured to: switch to one of a first state in which an input of a clock signal for operating an imager to the imager is permitted and a second state in which the input of the clock signal to the imager is prohibited, and temporarily switch from the first state to the second state when a first synchronization signal output from a first synchronization signal generation circuit and a second synchronization signal output from a second synchronization signal generation circuit are not synchronized.

Abstract: An imaging system according to the present disclosure has a camera unit and a control unit that are connected via a transmission cable having a power signal line and a video signal line. The camera unit includes an imaging element and a selector circuit. The control unit includes a supply voltage control circuit, a feedback value measurement circuit, and an arithmetic circuit that calculates a resistance value R3 related to a resistance value R1 of the video signal line and a resistance value R2 of the power signal line from the supply voltage Vctrl, the feedback voltage Vfb and the feedback current Ifb, and calculates a drive voltage Vcis based on the resistance value R2, the supply current Ictrl, and the supply voltage Vctrl.

Abstract: A signal processing device includes a processor including at least one or more pieces of hardware. The processor is configured to: when a first synchronization signal from a first synchronization signal generation circuit, the first synchronization signal generation circuit receiving a first clock signal and outputting the first synchronization signal, and a second synchronization signal output from a second synchronization signal generation circuit are not synchronized, reset the first synchronization signal generation circuit, and in a period in which the first synchronization signal generation circuit is reset, set a frequency of the first clock signal to be higher than a frequency in another period.

Abstract: A signal processing device includes: a processor including at least one or more pieces of hardware, the processor being configured to: switch to one of a first state in which an input of a clock signal for operating an imager to the imager is permitted and a second state in which the input of the clock signal to the imager is prohibited, and temporarily switch from the first state to the second state when a first synchronization signal output from a first synchronization signal generation circuit and a second synchronization signal output from a second synchronization signal generation circuit are not synchronized.