Patents by Inventor Daina Inoue
Daina Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150060985Abstract: According to one embodiment, nonvolatile semiconductor memory device includes: a semiconductor layer; element regions separated the semiconductor layer, the element regions; and a memory cell including a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode provided above the element regions, a peripheral region including a resistance element including a resistance element layer provided above the semiconductor layer via a first insulating film, a dummy layer provided on a part of the resistance element layer via a second insulating film, a third insulating film provided on the resistance element layer at a first distance from the dummy layer, a fourth insulating film provided on the semiconductor layer at a second distance from the resistance element layer, and a contact piercing the third insulating film, and connected to the resistance element layer, the first distance being shorter than the second distance.Type: ApplicationFiled: March 10, 2014Publication date: March 5, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Takashi Kobayashi, Daina Inoue, Hideto Takekida
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Patent number: 8592887Abstract: A semiconductor storage device includes an interlayer insulating film provided between select gate electrodes, a first fill material extending along upper portions of memory cell gate electrodes so as to cover air gaps residing between the memory cell gate electrodes, the first fill material extending along sidewalls of the select gate electrodes and sidewalls of the interlayer insulating film so as to define a recess above the first fill material extending along the sidewalls of the select gate electrodes and the sidewalls of the interlayer insulating film, a second fill material filling the recess above the first fill material, and a plurality of contacts formed through the interlayer insulating film, the contacts physically contacting each of device areas formed in a semiconductor substrate.Type: GrantFiled: December 21, 2011Date of Patent: November 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Daina Inoue, Hidenobu Nagashima, Akira Yotsumoto
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Patent number: 8460997Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.Type: GrantFiled: January 3, 2011Date of Patent: June 11, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiro Omura, Satoshi Nagashima, Katsunori Yahashi, Jungo Inaba, Daina Inoue
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Publication number: 20120256263Abstract: A semiconductor storage device includes an interlayer insulating film provided between select gate electrodes, a first fill material extending along upper portions of memory cell gate electrodes so as to cover air gaps residing between the memory cell gate electrodes, the first fill material extending along sidewalls of the select gate electrodes and sidewalls of the interlayer insulating film so as to define a recess above the first fill material extending along the sidewalls of the select gate electrodes and the sidewalls of the interlayer insulating film, a second fill material filling the recess above the first fill material, and a plurality of contacts formed through the interlayer insulating film, the contacts physically contacting each of device areas formed in a semiconductor substrate.Type: ApplicationFiled: December 21, 2011Publication date: October 11, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daina INOUE, Hidenobu Nagashima, Akira Yotsumoto
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Publication number: 20120061837Abstract: In a method of manufacturing a semiconductor device according to an embodiment, an etching stopper, an oxide film and a mask material are formed. A trench pattern is formed in the mask material. The oxide film is etched to form the trench pattern therein by using the mask material having the trench pattern formed therein as a mask. The etching stopper is etched until the etching stopper is penetrated to form the trench pattern therein, by using the oxide film having the trench pattern formed therein as a mask. A Cu film is formed to be filled in the trench pattern formed in the etching stopper and the oxide film and to cover the top surface of the oxide film. CMP is performed on the Cu film and the oxide film until the top surface of the etching stopper serving as a stopper is exposed.Type: ApplicationFiled: September 12, 2011Publication date: March 15, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Daina INOUE, Minori KAJIMOTO
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Publication number: 20120032266Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a memory cell region defined in the semiconductor substrate; and a line-and-space pattern formed in the memory cell region in which the lines constitute an active region and the spaces constitute an element isolation region. The first and the second lines of the active region counted from two opposing ends of the memory cell region are each separated into two or more line segments. The segment ends of the line segments of the first and the second lines are linked to form a loop by a linking pattern.Type: ApplicationFiled: August 4, 2011Publication date: February 9, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daina INOUE, Minori KAJIMOTO, Tatsuya KATO
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Publication number: 20110097888Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.Type: ApplicationFiled: January 3, 2011Publication date: April 28, 2011Inventors: Mitsuhiro Omura, Satoshi Nagashima, Katsunori Yahashi, Jungo Inaba, Daina Inoue
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Patent number: 7687387Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section beType: GrantFiled: August 18, 2008Date of Patent: March 30, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Jungo Inaba, Daina Inoue, Mutsumi Okajima
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Publication number: 20090096007Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.Type: ApplicationFiled: October 2, 2008Publication date: April 16, 2009Inventors: Mitsuhiro OMURA, Satoshi NAGASHIMA, Katsunori YAHASHI, Jungo INABA, Daina INOUE
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Publication number: 20090050951Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section Is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section beType: ApplicationFiled: August 18, 2008Publication date: February 26, 2009Inventors: Jungo Inaba, Daina Inoue, Mutsumi Okajima