Abstract: A semiconductor device includes a first transistor formed on a semiconductor substrate, and including a first channel region, and a first gate electrode formed on the first channel region, and a second transistor formed on the semiconductor substrate, and including a second channel region having a conductivity type identical to a conductivity type of the first channel region, and a second gate electrode formed on the second channel region and having a potential identical to a potential of the first gate electrode. A drain of the first transistor is electrically connected to a source of the second transistor. An absolute value of a threshold voltage of the first transistor is greater than an absolute value of a threshold voltage of the second transistor.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; an offset spacer formed on a side surface of the gate electrode; an inner sidewall formed on the side surface of the gate electrode with the offset spacer interposed therebetween, and having an L-shaped cross section; and an insulating film formed to cover the gate electrode, the offset spacer, the inner sidewall, and a part of the semiconductor region located laterally outward from the inner sidewall. The offset spacer includes an inner offset spacer formed on the side surface of the gate electrode and an outer offset spacer formed to cover the side surface of the gate electrode and the inner offset spacer. The outer offset spacer is in contact with a top end and outer side surface of the inner offset spacer.

Abstract: Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impurity diffusion regions 7B6 are connected through a shared contact 9A1 to a first-level interconnect M1H, and the gate electrode 5E and N-type impurity diffusion regions 7A6 are connected through a shared contact 9A2 to a first-level interconnect M1I. In this way, contact pad parts of the gate electrodes 5A through 5F can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.

Abstract: A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; an offset spacer formed on a side surface of the gate electrode; an inner sidewall formed on the side surface of the gate electrode with the offset spacer interposed therebetween, and having an L-shaped cross section; and an insulating film formed to cover the gate electrode, the offset spacer, the inner sidewall, and a part of the semiconductor region located laterally outward from the inner sidewall. The offset spacer includes an inner offset spacer formed on the side surface of the gate electrode and an outer offset spacer formed to cover the side surface of the gate electrode and the inner offset spacer. The outer offset spacer is in contact with a top end and outer side surface of the inner offset spacer.

Abstract: In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.

Abstract: An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.

Abstract: A semiconductor device includes a first conductivity type well formed on a semiconductor substrate, and a first transistor and a second transistor formed on the well. The first transistor has first pocket regions containing a first conductivity type impurity and first source/drain regions containing a second conductivity type impurity, and the second transistor has second pocket regions containing a first conductivity type impurity and second source/drain regions containing a second conductivity type impurity, and executes an analog function. A concentration of the first conductivity type impurity contained in the source-side and the drain-side second pocket regions is lower than a concentration of the first conductivity type impurity included in the first pocket regions.

Abstract: An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.

Abstract: A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.

Abstract: The effective distance Deff_i between a well boundary and an active region of a transistor is used as a parameter for expressing a well proximity effect. For example, a delay library is created using the rising time Tslew of a signal input to the gate, load capacitance Cload at the output side and Deff_i. The use of the effective distance Deff_i between the well boundary and the transistor allows very simple modeling to be accurately performed, so that a gate-level simulation considering a well proximity effect at an LSI level is enabled.

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract: By using, as a model expression, an expression showing an inverse proportion between a change rate ?Idsat/Idsat of saturated current value and a product of a gate protrusion length E1 and a gate width Wg of a transistor and a coefficient, modeling is executed for a transistor property that depends on the gate protrusion length. This provides a circuit simulation that takes into consideration the gate protrusion length of a gate electrode.

Abstract: A semiconductor evaluation device evaluates an amount of mask misalignment in an optical exposure step during the fabrication of a semiconductor device. The semiconductor evaluation device has a first semiconductor region selectively formed in a semiconductor substrate, a first gate electrode having a cross-shaped plan configuration, formed on the first semiconductor region with a first gate insulating film interposed therebetween, and an intersecting portion at which a first gate portion disposed in an X-axis direction and a second gate portion disposed in a Y-axis direction intersect each other, and a first impurity diffusion layer formed in the area of the first semiconductor region which is other than the portion thereof underlying the first gate electrode and partitioned by the first gate electrode into four diffusion regions.

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract: In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.

Abstract: In designing a semiconductor integrated circuit, circuit information used for circuit simulation is extracted from measurement values of electric characteristics of a device included in TEG and parameters included in a netlist are modified using the measurement values and simulation values. Circuit simulation is carried out using the thus modified netlist to lead to a decrease in error in the circuit simulation which is caused due to difference between design dimension and actual finished dimension, thereby preventing an increase in design margin and a yield lowering by malfunction.

Abstract: A method for designing a semiconductor integrated circuit includes: a step (a) of setting basic patterns including a plurality of active region/gate patterns each including a gate and an active region and a dummy gate while taking account of patterns of gates on the respective sides of each gate; a step (b) of forming a plurality of basic pattern combinations by combining some of the basic patterns; and a step (c) of forming a standard cell by combining some of the plurality of basic pattern combinations. The plurality of basic pattern combinations include a single transistor (large width), a single transistor (small width), and parallel connected N transistors (large width), for example.

Abstract: A first-conductive-type doped layer is provided on a second-conductive-type well, and a gate electrode of a MOS transistor and the first-conductive-type doped layer are connected to each other via a plug for filling a contact hole and a metal interconnect of Cu. Furthermore, a second-conductive-type doped layer is provided on a first-conductive-type well, and a gate electrode of a MOS transistor and the second-conductive-type doped layer are connected to each other via a plug for filling a contact hole and a metal interconnect of Cu. Then, a first diode and a second diode are provided between the gate electrode and the second-conductive-type well and between the gate electrode and the first-conductive-type well, respectively. Thus, antenna damage generated in the gate electrodes of the MOS transistors is prevented.