Patents by Inventor Daisuke Saida

Daisuke Saida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230229953
    Abstract: Provided are a computer system and a control device, which are capable of reducing the necessity for reconfiguration according to the computation details in the circuit configuration of a quantum computer. The computer system includes an acquisition unit 122 that acquires computation details; a group of computation units including a plurality of computation units each configured to execute computation using quantum effects or thermal effects in a superconducting state; a selection unit 124 that selects a computation unit from the group of computation units based on the computation details; and an execution unit 212 that causes the computation unit selected by the selection unit to execute computation.
    Type: Application
    Filed: June 4, 2021
    Publication date: July 20, 2023
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventor: Daisuke SAIDA
  • Patent number: 10481975
    Abstract: A memory system has a non-volatile memory, an error corrector, an error information storage, and an access controller. The non-volatile memory comprising a plurality of memory cells. The error corrector to correct an error included in data read from the non-volatile memory. The error information storage, based on an error rate when a predetermined number or more of data is written in the non-volatile memory and read therefrom, to store first information on whether there is an error in the written data, on whether there is an error correctable by the error corrector in the written data, and on whether there is an error uncorrectable by the error corrector in the written data. The access controller, based on the first information, to control at least one of reading from or writing to the non-volatile memory.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: November 19, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Saida, Hiroki Noguchi, Keiko Abe, Shinobu Fujita
  • Patent number: 10388350
    Abstract: A memory system has a nonvolatile memory having a plurality of readable and writable memory cells, a write voltage control unit that controls at least one of a voltage value and a pulse width of a write voltage of the nonvolatile memory in accordance with a weight of a signal processing path or a signal processing node, a write unit that writes data in two or more memory cell groups among the plurality of memory cells using the write voltage controlled by the write voltage control unit, a reversal probability detection unit that detects a reversal probability of the memory cell group when writing data is written by the write unit, and a weight conversion unit that converts the detected reversal probability into a weight.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 20, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Yousuke Isowaki, Michael Arnaud Quinsat, Kenichiro Yamada, Kosuke Tatsumura
  • Publication number: 20190035449
    Abstract: A memory system has a nonvolatile memory having a plurality of readable and writable memory cells, a write voltage control unit that controls at least one of a voltage value and a pulse width of a write voltage of the nonvolatile memory in accordance with a weight of a signal processing path or a signal processing node, a write unit that writes data in two or more memory cell groups among the plurality of memory cells using the write voltage controlled by the write voltage control unit, a reversal probability detection unit that detects a reversal probability of the memory cell group when writing data is written by the write unit, and a weight conversion unit that converts the detected reversal probability into a weight.
    Type: Application
    Filed: March 5, 2018
    Publication date: January 31, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke SAIDA, Yousuke ISOWAKI, Michael Arnaud QUINSAT, Kenichiro YAMADA, Kosuke TATSUMURA
  • Patent number: 10103198
    Abstract: A magnetoresistive element according to an embodiment includes: a multilayer structure including a first magnetic layer, a second magnetic layer disposed above the first magnetic layer, and a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a conductor disposed above the second magnetic layer, and including a lower face, an upper face opposing to the lower face, and a side face that is different from the lower face and the upper face, an area of the lower face of the conductor being smaller than an area of the upper face of the conductor, and smaller than an area of an upper face of the second magnetic layer; and a carbon-containing layer disposed on the side face of the conductor.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: October 16, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Saori Kashiwada, Yuichi Ohsawa, Daisuke Saida, Chikayoshi Kamata, Kazutaka Ikegami, Megumi Yakabe, Hiroaki Maekawa
  • Patent number: 10096771
    Abstract: According to one embodiment, a magnetic element includes a first stacked unit and a third ferromagnetic layer. The first stacked unit includes first and second ferromagnetic layers, and a first non-magnetic layer. The first ferromagnetic layer has a first magnetization. The second ferromagnetic layer is separated from the first ferromagnetic layer in a first direction, and has a second magnetization. The first non-magnetic layer is provided between the first and second ferromagnetic layers. The third ferromagnetic layer is stacked with the first stacked unit in the first direction, and has a third magnetization. 2?NzMs is not less than 0.9 times of a magnetic resonance frequency (Hz) of the third ferromagnetic layer, when the second magnetization is Ms (emu/cc), a demagnetizing coefficient of the second ferromagnetic layer is Nz, and a gyro magnetic constant is ? (Hz/Oe).
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 9, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Daisuke Saida
  • Publication number: 20180267853
    Abstract: A memory system has a non-volatile memory, an error corrector, an error information storage, and an access controller. The non-volatile memory comprising a plurality of memory cells. The error corrector to correct an error included in data read from the non-volatile memory. The error information storage, based on an error rate when a predetermined number or more of data is written in the non-volatile memory and read therefrom, to store first information on whether there is an error in the written data, on whether there is an error correctable by the error corrector in the written data, and on whether there is an error uncorrectable by the error corrector in the written data. The access controller, based on the first information, to control at least one of reading from or writing to the non-volatile memory.
    Type: Application
    Filed: September 8, 2017
    Publication date: September 20, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke SAIDA, Hiroki NOGUCHI, Keiko ABE, Shinobu FUJITA
  • Patent number: 9959919
    Abstract: A memory system has a non-volatile memory of which access speed is electrically controlled, a control circuitry that selects a first region which is a portion of a memory region of the non-volatile memory, and a boost circuit that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 1, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Susumu Takeda, Hiroki Noguchi, Kazuhiko Abe
  • Patent number: 9935260
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer, a second magnetic layer, a third magnetic layer, and a first non-magnetic layer. The third magnetic layer is provided between a first part of the first magnetic layer and the second magnetic layer. The first non-magnetic layer is provided between the second magnetic layer and the third magnetic layer. The first magnetic layer further includes a second part. At least a portion of the second part overlaps at least a portion of the third magnetic layer in a second direction orthogonal to a first direction from the first part toward the second magnetic layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: April 3, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Shogo Itai, Chikayoshi Kamata
  • Patent number: 9882122
    Abstract: According to one embodiment, a memory device includes a stacked structure and a controller. The stacked structure includes a first magnetic layer, a second magnetic layer stacked with the first magnetic layer, and a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The second magnetic layer includes a first portion and a second portion stacked with the first portion. A magnetic resonance frequency of the first portion is different from a magnetic resonance frequency of the second portion. The controller is electrically connected to the stacked structure and causes a pulse current to flow in the stacked body in a first period. A length of the first period is not less than 0.9 times and not more than 1.1 times the absolute value of an odd number times of the reciprocal of a magnetic resonance frequency of the second magnetic layer.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 30, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Naoharu Shimomura
  • Patent number: 9818464
    Abstract: According to one embodiment, a magnetic memory element includes a stacked structure. The stacked structure includes a first and a second stacked member. The first stacked member includes a first and second ferromagnetic layer. A magnetic resonance frequency of the second ferromagnetic layer is a first frequency. A direction of a magnetization of the second ferromagnetic layer is settable to a direction of a first current when a magnetic field of the first frequency is applied to the first stacked member and the first current flows in the first stacked member. The direction of the magnetization of the second ferromagnetic layer does not change when the second current smaller than the first current flows in the first stacked member. The second stacked member includes a third ferromagnetic layer. A magnetization of the third ferromagnetic layer can generate a magnetic field of the first frequency by the second current.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: November 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Minoru Amano, Jyunichi Ozeki, Naoharu Shimomura
  • Publication number: 20170279037
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer, a second magnetic layer, a third magnetic layer, and a first non-magnetic layer. The third magnetic layer is provided between a first part of the first magnetic layer and the second magnetic layer. The first non-magnetic layer is provided between the second magnetic layer and the third magnetic layer. The first magnetic layer further includes a second part. At least a portion of the second part overlaps at least a portion of the third magnetic layer in a second direction orthogonal to a first direction from the first part toward the second magnetic layer.
    Type: Application
    Filed: September 14, 2016
    Publication date: September 28, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke SAIDA, Shogo ITAI, Chikayoshi KAMATA
  • Patent number: 9722173
    Abstract: According to one embodiment, a memory device includes a stacked body and a controller. The stacked body includes a first magnetic layer, a second magnetic layer stacked with the first magnetic layer, and a first nonmagnetic layer provided between the first magnetic layer and the second ferromagnetic layer. The second ferromagnetic layer includes a first portion and a second portion stacked with the first portion. The controller causes a current to flow in the stacked body in a programming period. The programming period includes a first and a second period. The current has a first value in the first period and a second value in the second period. The second value is less than the first value.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 1, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Naoharu Shimomura
  • Patent number: 9620189
    Abstract: A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a tunnel barrier layer located between the first and second magnetic layers; a first electrode provided on a first surface of the magnetic multilayer structure; a second electrode provided on a second surface of the magnetic multilayer structure; an insulating film provided on a side surface of the magnetic multilayer structure; and a control electrode provided on the side surface of the magnetic multilayer structure with the insulating film located therebetween, a voltage being applied to the control electrode in a read operation, which increases an energy barrier for changing the magnetization of the second magnetic layer.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: April 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoharu Shimomura, Eiji Kitagawa, Minoru Amano, Daisuke Saida, Kay Yakushiji, Takayuki Nozaki, Shinji Yuasa, Akio Fukushima, Hiroshi Imamura, Hitoshi Kubota
  • Publication number: 20170077394
    Abstract: According to one embodiment, a magnetic element includes a first stacked unit and a third ferromagnetic layer. The first stacked unit includes first and second ferromagnetic layers, and a first non-magnetic layer. The first ferromagnetic layer has a first magnetization. The second ferromagnetic layer is separated from the first ferromagnetic layer in a first direction, and has a second magnetization. The first non-magnetic layer is provided between the first and second ferromagnetic layers. The third ferromagnetic layer is stacked with the first stacked unit in the first direction, and has a third magnetization. 2?NzMs is not less than 0.9 times of a magnetic resonance frequency (Hz) of the third ferromagnetic layer, when the second magnetization is Ms (emu/cc), a demagnetizing coefficient of the second ferromagnetic layer is Nz, and a gyro magnetic constant is ? (Hz/Oe).
    Type: Application
    Filed: September 12, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Daisuke SAIDA
  • Publication number: 20160379698
    Abstract: According to one embodiment, a magnetic memory element includes a stacked structure. The stacked structure includes a first and a second stacked member. The first stacked member includes a first and second ferromagnetic layer. A magnetic resonance frequency of the second ferromagnetic layer is a first frequency. A direction of a magnetization of the second ferromagnetic layer is settable to a direction of a first current when a magnetic field of the first frequency is applied to the first stacked member and the first current flows in the first stacked member. The direction of the magnetization of the second ferromagnetic layer does not change when the second current smaller than the first current flows in the first stacked member. The second stacked member includes a third ferromagnetic layer. A magnetization of the third ferromagnetic layer can generate a magnetic field of the first frequency by the second current.
    Type: Application
    Filed: September 13, 2016
    Publication date: December 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke SAIDA, Minoru AMANO, Jyunichi OZEKI, Naoharu SHIMOMURA
  • Publication number: 20160365509
    Abstract: According to one embodiment, a memory device includes a stacked body and a controller. The stacked body includes a first magnetic layer, a second magnetic layer stacked with the first magnetic layer, and a first nonmagnetic layer provided between the first magnetic layer and the second ferromagnetic layer. The second ferromagnetic layer includes a first portion and a second portion stacked with the first portion. The controller causes a current to flow in the stacked body in a programming period. The programming period includes a first and a second period. The current has a first value in the first period and a second value in the second period. The second value is less than the first value.
    Type: Application
    Filed: August 26, 2016
    Publication date: December 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke SAIDA, Naoharu SHIMOMURA
  • Publication number: 20160365508
    Abstract: According to one embodiment, a memory device includes a stacked structure and a controller. The stacked structure includes a first magnetic layer, a second magnetic layer stacked with the first magnetic layer, and a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The second magnetic layer includes a first portion and a second portion stacked with the first portion. A magnetic resonance frequency of the first portion is different from a magnetic resonance frequency of the second portion. The controller is electrically connected to the stacked structure and causes a pulse current to flow in the stacked body in a first period. A length of the first period is not less than 0.9 times and not more than 1.1 times the absolute value of an odd number times of the reciprocal of a magnetic resonance frequency of the second magnetic layer.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Naoharu Shimomura
  • Publication number: 20160276008
    Abstract: A memory system has a non-volatile memory of which access speed is electrically controlled, a control circuitry that selects a first region which is a portion of a memory region of the non-volatile memory, and a boost circuit that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region.
    Type: Application
    Filed: March 11, 2016
    Publication date: September 22, 2016
    Inventors: Daisuke SAIDA, Susumu Takeda, Hiroki Noguchi, Kazuhiko Abe
  • Publication number: 20160268338
    Abstract: A magnetoresistive element according to an embodiment includes: a multilayer structure including a first magnetic layer, a second magnetic layer disposed above the first magnetic layer, and a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a conductor disposed above the second magnetic layer, and including a lower face, an upper face opposing to the lower face, and a side face that is different from the lower face and the upper face, an area of the lower face of the conductor being smaller than an area of the upper face of the conductor, and smaller than an area of an upper face of the second magnetic layer; and a carbon-containing layer disposed on the side face of the conductor.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Saori KASHIWADA, Yuichi Ohsawa, Daisuke Saida, Chikayoshi Kamata, Kazutaka Ikegami, Megumi Yakabe, Hiroaki Maekawa