Patents by Inventor Daitei Shin

Daitei Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5976618
    Abstract: A process capable of forming an inorganic film which can be used at a relatively large thickness equivalent to, or greater than, the thickness of an organic SOG, without being subjected to oxidation by O.sub.2 plasma treatment used in a fabrication process of a semiconductor device. Polysilazane is first coated on a base, and the resulting polysilazane film is converted to a silicon dioxide film.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: November 2, 1999
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Shun-ichi Fukuyama, Daitei Shin, Yuki Komatsu, Hideki Harada
  • Patent number: 5770260
    Abstract: A process capable of forming an inorganic film which can be used at a relatively large thickness equivalent to, or greater than, the thickness of an organic SOG, without being subjected to oxidation by O.sub.2 plasma treatment used in a fabrication process of a semiconductor device. Polysilazane is first coated on a base, and the resulting polysilazane film is converted to a silicon dioxide film.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: June 23, 1998
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Shun-ichi Fukuyama, Daitei Shin, Yuki Komatsu, Hideki Harada, Yoshihiro Nakata, Michiko Kobayashi, Yoshiyuki Okura
  • Patent number: 5310720
    Abstract: A thick planarization layer of silicon dioxide that is heat resistant is provided by coating a polysilazane layer over a substrate having steps and firing the polysilazane layer in an oxygen-containing atmosphere to convert the polysilazane to silicon dioxide. The temperature of this conversion may be as low as 400.degree. to 450.degree. C. while a higher firing or curing temperature is preferable to obtain a more densified oxide layer.
    Type: Grant
    Filed: February 24, 1993
    Date of Patent: May 10, 1994
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Daitei Shin, Hideki Harada
  • Patent number: 5288655
    Abstract: A dynamic random access memory comprises a memory cell region and a sense amplifier region defined on a substrate, a first insulation layer provided on the semiconductor substrate to cover both the memory cell region and the sense amplifier region, a first conductor pattern provided on the first insulation layer, an intermediate connection pattern provided on the first insulation layer in correspondence to the sense amplifier region, a spin-on-glass layer provided on the first insulation layer to extend over both the memory cell region and the sense amplifier region, and a projection part provided on the substrate of the sense amplifier region in correspondence to the intermediate connection pattern under the first insulation layer for lifting the level of the surface of the first insulation layer such that the intermediate interconnection pattern is exposed above the upper major surface of the spin-on-glass layer.
    Type: Grant
    Filed: April 21, 1993
    Date of Patent: February 22, 1994
    Assignee: Fujitsu Limited
    Inventors: Masaaki Higasitani, Daitei Shin, Toshio Nomura
  • Patent number: 5245205
    Abstract: A dynamic random access memory comprises a memory cell region and a sense amplifier region defined on a substrate, a plurality of memory cell capacitors provided on the memory cell region in correspondence to memory cell transistors, a first insulation layer provided on the semiconductor substrate to cover both the memory cell region and the sense amplifier region, a first conductor pattern provided on the first insulation layer, an intermediate connection pattern provided on the first insulation layer in correspondence to the sense amplifier region, a spin-on-glass layer provided on the first insulation layer to extend over both the memory cell region and the sense amplifier region, and a projection part provided on the substrate of the sense amplifier region in correspondence to the intermediate connection pattern under the first insulation layer for lifting the level of the surface of the first insulation layer such that the intermediate interconnection pattern is exposed above the upper major surface of t
    Type: Grant
    Filed: September 19, 1991
    Date of Patent: September 14, 1993
    Assignee: Fujitsu Limited
    Inventors: Masaaki Higasitani, Daitei Shin, Toshio Nomura