Abstract: The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal. Additionally, in other embodiments, the timing signal associated with various DUTs is used as a timing reference for other devices.

Abstract: The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal. Additionally, in other embodiments, the timing signal associated with various DUTs is used as a timing reference for other devices.

Abstract: A system for testing a device includes a processor that operates to execute instructions, where the instructions are used to test a device. The processor also operates to generate test signals associated with the test instructions. An interface apparatus is coupled to the processor and operates to communicate the test signals to the device. The interface apparatus includes connectors, where each connector operates to communicate at least one of the test signals.

Abstract: According to one embodiment of the invention, a system for testing electronic devices includes a first RF source operable to output a first signal, a second RF source operable to output a second signal, a combiner coupled to the first and second RF sources and operable to combine the first and second signals to create a third signal, one or more down converters operable to receive respective output signals from respective electronic devices and create respective down converted signals, and a set of switches operable to switch the second RF source to a local oscillator function that couples to the one or more down converters for inputting respective reference signals into the one or more down converters.

Abstract: The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal. Additionally, in other embodiments, the timing signal associated with various DUTs is used as a timing reference for other devices.

Abstract: A method for measuring noise parameters includes generating a noise signal at a noise source. The noise signal includes a first input signal at a first frequency and a second input signal at a second frequency. The first input signal and the second input signal are modulated onto a carrier to generate a modulated signal. The modulated signal is attenuated to a desired power level and applied to a device under test to obtain a noise measurement.

Abstract: A method for measuring noise parameters includes generating a noise signal at a noise source. The noise signal includes a first input signal at a first frequency and a second input signal at a second frequency. The first input signal and the second input signal are modulated onto a carrier to generate a modulated signal. The modulated signal is attenuated to a desired power level and applied to a device under test to obtain a noise measurement.

Abstract: According to one embodiment of the invention, a system for testing electronic devices includes a first RF source operable to output a first signal, a second RF source operable to output a second signal, a combiner coupled to the first and second RF sources and operable to combine the first and second signals to create a third signal, one or more down converters operable to receive respective output signals from respective electronic devices and create respective down converted signals, and a set of switches operable to switch the second RF source to a local oscillator function that couples to the one or more down converters for inputting respective reference signals into the one or more down converters.

Abstract: The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal. Additionally, in other embodiments, the timing signal associated with various DUTs is used as a timing reference for other devices.

Abstract: A system for testing a device includes a processor that operates to execute instructions, where the instructions are used to test a device. The processor also operates to generate test signals associated with the test instructions. An interface apparatus is coupled to the processor and operates to communicate the test signals to the device. The interface apparatus includes connectors, where each connector operates to communicate at least one of the test signals.

Abstract: The present invention provides a system and method for high resolution current measurements of an integrated circuit (13). With the present invention, no DFT circuits are required. Leakage current characterizing an integrated circuit is determined for at least one logic state of the integrated circuit from a sum of a first and second current measurement. A voltage source (15) and a current source (17) are used at different settings for each measurement and the measurements are summed for evaluation with an expected value.

Abstract: The present invention provides a system and method for high resolution current measurements of an integrated circuit (13). With the present invention, no DFT circuits are required. Leakage current characterizing an integrated circuit is determined for at least one logic state of the integrated circuit from a sum of a first and second current measurement. A voltage source (15) and a current source (17) are used at different settings for each measurement and the measurements are summed for evaluation with an expected value.

Abstract: The bandwidth of a bipolar complementary emitter follower unity gain buffer is proportionally dependent upon the idle current of the input stage (Q1, Q2) that drives the base nodes of the NPN (Q3) and PNP (Q4) emitter follower output transistors. A high bandwidth typically requires a high idle current. The bandwidth and slew rate of a unity gain buffer are improved without increasing the idle circuit by adding a circuit (Q9-Q12)to sense when a transient is occurring and increasing the positive or negative bias current only during the positive or negative transient. Shunt diodes (Q5, Q6) (base-emitter junctions) can be added across the input transistor emitters to shunt some of the input stage idle current into the opposing current source. This will reduce the idle current at the output stage and reduce the power dissipation of the input stage without sacrificing the available current to drive the base nodes of the output transistors.

Abstract: The frequency response of a differential amplifier or comparator is improved by adding a positive and negative clamp at the collector (drain in the case of an MOS embodiment) outputs of the differential transistor pair that will clamp the output voltage swing to less than one RC time constant. The frequency response (rise time t.sub.r) is improved from t.sub.r =2.2.times.RC to t.sub.r <<1.times.RC. The differential output resistors can be increased to improve the differential gain while maintaining an improved rise time of t.sub.r <<1.times.RC.

Abstract: An impedance matching circuit which includes an RC network placed at the end of the transmission line and which will absorb reflections. The values of the resistor and capacitor are selected such that the output voltage at the end of the transmission line is attenuated only during the duration of the reflected waves and the overall gain from the incident signal to the end of the transmission line is 1:1. The values of the resistor and capacitor selected are based upon the impedance mismatch and the length of the transmission line.

Abstract: Field Effect Transistors are used to replace mechanical relays and to minimize the distance a Device Under Test (DUT) must drive a signal path to the receiver, to minimize insertion losses in critical paths to the DUT, and generally increase reliability in integrated test systems by eliminating the need for relays to test integrated circuits.

Abstract: Hysteresis effects in low frequency field effect transistor circuits are minimized by using biasing or clamping circuits including field effect transistors.

Abstract: Disclosed is a device power supply in a semiconductor test system for supplying programmed test pattern voltages to a semiconductor device under test and for current range switching of current range resistors without effecting the output voltage of the device power supply.