Abstract: An error detector circuit and associated method for a digital receiver. The digital receiver is operative in a TDMA communication scheme in which DQPSK-modulated signals are generated, such as the Japanese Digital Cordless Telephone System. The error detector circuit detects times in which an excessive amount of noise or other distortion is introduced upon one or more sequences of a signal transmitted during one or more time slots in the TDMA communications scheme. A receiver incorporating the error detector circuit is operative not to decode portions of a received signal when excessive numbers of sequences include excessive amounts of noise or other distortion introduced thereupon. Thereby, degradation of the audio quality of a signal actually recreated by the receiver incorporating the error detector.

Abstract: A gain control circuit for a radio transmitter, such as the radio transmitter portion of a radiotelephone operative to transmit a .pi./4 DQPSK-modulated signal in discrete bursts. The signal portion of the signal transmitted during each discrete burst forms a slot and at least one of the slots includes a pre-determined data sequence portion. The peak power level of the portion of the slot comprising the pre-determined data sequence portion, once amplified by amplifier circuitry of the radiotelephone, is compared with a stored value representative of the peak power level of a corresponding portion of a slot amplified to be of a desired signal level. Responsive to such comparison, the amplification level of the amplifier circuitry is altered.