Abstract: A voltage regulator circuit that regulates voltage on an output node that provides power to a load circuit having varying current draw. A feedback voltage from the output node is compared to reference voltages. In response to the comparisons, pull-up/down circuits are applied to a gate-control node connected to the gate of a pass transistor. The voltage of the gate-control node is adjusted by integrating current from the pull-up/down circuits. In response to the feedback voltage being between the first and second reference voltages, the voltage on the gate-control node is maintained by disabling the pull-up/down circuits at the gate-control node.

Abstract: A voltage regulator has an output driver current mirror circuit and one or more control circuits. The output driver current mirror circuit includes an output driver transistor, a tunable resistance circuit, and a diode-connected transistor. The output driver transistor has one current electrode coupled to a supply voltage and another current electrode coupled to an output terminal for providing the output voltage of the voltage regulator. The tunable resistance circuit has one terminal coupled to a control electrode of the output driver transistor, and another terminal coupled to a current electrode of the diode-connected transistor. The one or more control circuits includes a comparator for controlling a current provided to the output driver current mirror in response to a feedback signal from the output terminal.

Abstract: A voltage regulator circuit that regulates voltage on an output node that provides power to a load circuit having varying current draw. A feedback voltage from the output node is compared to reference voltages. In response to the comparisons, pull-up/down circuits are applied to a gate-control node connected to the gate of a pass transistor. The voltage of the gate-control node is adjusted by integrating current from the pull-up/down circuits. In response to the feedback voltage being between the first and second reference voltages, the voltage on the gate-control node is maintained by disabling the pull-up/down circuits at the gate-control node.

Abstract: A voltage regulator has an output driver current mirror circuit and one or more control circuits. The output driver current mirror circuit includes an output driver transistor, a tunable resistance circuit, and a diode-connected transistor. The output driver transistor has one current electrode coupled to a supply voltage and another current electrode coupled to an output terminal for providing the output voltage of the voltage regulator. The tunable resistance circuit has one terminal coupled to a control electrode of the output driver transistor, and another terminal coupled to a current electrode of the diode-connected transistor. The one or more control circuits includes a comparator for controlling a current provided to the output driver current mirror in response to a feedback signal from the output terminal.

Abstract: A fully differential peak detection circuit includes programmable sensitivity and an autozero function. The peak detector has a fully differential charge-coupled analog signal path. The entire analog signal path is autozeroed upon enable and/or in response to sensing a logic zero at the output, where the logic zero follows a logic one. The peak detector includes a differential gain stage for receiving an analog input signal. The differential gain stage includes offset error compensation. The offset error compensation is selected upon enable and/or in response to an output signal of the peak detection circuit and automatically zeros an offset error voltage in response to a predetermined logic state of the output signal. The output of the gain stage is provided to a comparator stage. A plurality of capacitors coupled to the comparator stage stores a predetermined voltage for setting a sensitivity of the peak detector.

Abstract: A design-for-test (DFT) circuit for an integrated circuit (IC) for enabling accurate quiescent current testing. The IC includes a voltage supply pin, a ground pin and an internal voltage regulator coupled between the voltage supply and ground pins for providing an internal output voltage. The DFT circuit includes a voltage storage device which couples to the voltage regulator to temporarily maintain the internal output voltage when the voltage regulator is disabled. The mode control circuit detects a quiescent current test mode, disables the voltage regulator and decouples the voltage regulator from the voltage storage device when the quiescent current test mode is detected. The DFT circuit may include an enable circuit which generates a freeze signal when the quiescent current test mode is detected, and at least one switch which decouples the voltage regulator from the voltage storage node. The DFT circuit is particularly useful for low pin-count ICs.

Abstract: A reference circuit provides a reference voltage and a reference current that are both temperature and a power supply voltage independent. The reference circuit includes a bandgap reference circuit, a current source, and a resistor. The bandgap reference circuit provides a feedback voltage to control the current source and thereby generate a temperature independent voltage and a PTAT (proportional to absolute temperature) current. A resistor having a positive temperature coefficient is coupled to the feedback controlled current source to provide a CTAT (complementary to absolute temperature) current. The CTAT current is summed directly into the feedback controlled current source to produce a reference current that is substantially constant over a range of temperatures.

Abstract: A programmable capacitor array does not require separate switching transistors because the capacitors themselves have a switchable capacitance, which capacitors are made in the manner of regular N channel transistors with their source/drains connected to each other. When a logic low is applied to the gate, the capacitance is relatively low and the capacitance is what is commonly called parasitic capacitance. The capacitance increases significantly when a logic high is applied to the gate because the logic high has the effect of inverting the channel. Thus, the capacitor array is made of transistors that themselves have switchable capacitance operated so that no separate switching transistors are required. This allows for construction of an array of unit capacitors to achieve monotonic operation and good linearity using conventional manufacturing of N channel transistors while achieving significant area savings and reduced power consumption.