Abstract: A source network device may receive a multicast data stream to be provided to a plurality of network devices of a network, and may generate, for the multicast data stream, a segment routing header that identifies the plurality of network devices to be provided the multicast data stream. The source network device may cause the multicast data stream to be serially provided to the plurality of network devices identified in the segment routing header without requiring the plurality of network devices to store and reconstruct the segment routing header and without requiring the plurality of network devices to maintain state.

Abstract: A source network device may receive a multicast data stream to be provided to a plurality of network devices of a network, and may generate, for the multicast data stream, a segment routing header that identifies the plurality of network devices to be provided the multicast data stream. The source network device may cause the multicast data stream to be serially provided to the plurality of network devices identified in the segment routing header without requiring the plurality of network devices to store and reconstruct the segment routing header and without requiring the plurality of network devices to maintain state.

Abstract: A valve for a brake cooling system may include a body including a first and a second end, a first at least one radial passage, and a second at least one radial passage fluidly communicable with the first end. A first seat may be disposed within the body proximate the first end, while a plug may include a stop, a collar, and a first trunk disposed between the stop and the collar. The collar and the first trunk may be disposed in the body while an adapter may include a second seat, a head, and a second trunk disposed between the second seat and the head. The second seat and the second trunk may be disposed in the plug with a chamber, fluidly communicable with the adapter and the first at least one radial passage, being defined in the first trunk of the plug. An actuator may be slidably disposed in the chamber, and be in operative association with a biasing member. A poppet may be in operative association with the biasing member and the first seat.

Abstract: A valve for a brake cooling system may include a body including a first and a second end, a first at least one radial passage, and a second at least one radial passage fluidly communicable with the first end. A first seat may be disposed within the body proximate the first end, while a plug may include a stop, a collar, and a first trunk disposed between the stop and the collar. The collar and the first trunk may be disposed in the body while an adapter may include a second seat, a head, and a second trunk disposed between the second seat and the head. The second seat and the second trunk may be disposed in the plug with a chamber, fluidly communicable with the adapter and the first at least one radial passage, being defined in the first trunk of the plug. An actuator may be slidably disposed in the chamber, and be in operative association with a biasing member. A poppet may be in operative association with the biasing member and the first seat.

Abstract: A motion determination system is disclosed. The system may receive a first and a second camera image from a camera, the first camera image received earlier than the second camera image. The system may identify corresponding features in the first and second camera images. The system may receive range data comprising at least one of a first and a second range data from a range detection unit, corresponding to the first and second camera images, respectively. The system may determine first positions and the second positions of the corresponding features using the first camera image and the second camera image. The first positions or the second positions may be determined by also using the range data. The system may determine a change in position of the machine based on differences between the first and second positions, and a VO-based velocity of the machine based on the determined change in position.

Abstract: The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the parallel subword compare operations can be stored at that bit position within the respective subword location of a result register. Alternatively, for a shifting-type instruction, pre-existing contents of a result register can be shifted one bit toward greater significance while the results are of the present operation are stored in the least-significant bits of respective result-register subword locations. This approach provides the results of multiple parallel subword compare instructions to be combined with relatively few instructions and reduces the maximum lateral movement of information—both of which can enhance performance.

Abstract: A motion determination system is disclosed. The system may receive a first and a second camera image from a camera, the first camera image received earlier than the second camera image. The system may identify corresponding features in the first and second camera images. The system may receive range data comprising at least one of a first and a second range data from a range detection unit, corresponding to the first and second camera images, respectively. The system may determine first positions and the second positions of the corresponding features using the first camera image and the second camera image. The first positions or the second positions may be determined by also using the range data. The system may determine a change in position of the machine based on differences between the first and second positions, and a VO-based velocity of the machine based on the determined change in position.

Abstract: In one embodiment, the present invention includes a method for receiving a data access instruction and obtaining an index into a data access hint register (DAHR) register file of a processor from the data access instruction, reading hint information from a register of the DAHR register file accessed using the index, and performing the data access instruction using the hint information. Other embodiments are described and claimed.

Abstract: A data processor includes an instruction decoder, an execution unit, a general-purpose register file, and an index-register file. The instruction set for the data processor includes indirect-indexing instructions to facilitate table lookups. When executing such an instruction, the execution unit reads an index stored at an index-register location specified by the instruction. The index refers to a general-purpose register location, which is then read and copied to a general-purpose register location as specified by the instruction. The disclosed execution unit includes four functional units, each with two read ports and a write port so that eight table lookups can be performed in parallel.

Abstract: The present invention provides a system and method for runtime updating of hints in program instructions. The invention also provides for programs of instructions that include hint performance data. Also, the invention provides an instruction cache that modifies hints and writes them back. As runtime hint updates are stored in instructions, the impact of the updates is not limited by the limited memory capacity local to a processor. Also, there is no conflict between hardware and software hints, as they can share a common encoding in the program instructions.

Abstract: Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.

Abstract: The present invention provides a system with a cache that indicates which, if any, of its sections contain data having spent status. The invention also provides a method for identifying cache sections containing data having spent status and then purging without writing back to main memory a cache line having at least one section containing data having spent status. The invention further provides a program that specifies a cache-line section containing data that is to acquire “spent” status. “Spent” data, herein, is useless modified or unmodified data that was formerly at least potentially useful data when it was written to a cache. “Purging” encompasses both invalidating and overwriting.

Abstract: Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.

Abstract: Motion estimation uses tally (Population Count) and XOR (or other bit-wise comparison) operations to obtain a block-match measure for reference and predicted blocks to identify motion vectors for use in video compression. The XOR operations can be performed on absolute or relative luminance data. For example, a one-bit-per-pixel representation of a block can indicate for each pixel its luminance relative to a local average luminance. The performance improvement offered by the invention (relative to methods using the absolute value of the differences of absolute luminance values) can more than offset a penalty in block-match accuracy due to loss of information in luminance data reduction and/or the ignoring of bit significance due to the bit-wise comparison.

Abstract: A technique to improve the performance of virtualized input/output (I/O) resources of a microprocessor within a virtual machine environment. More specifically, embodiments of the invention enable accesses of virtualized I/O resources to be made by guest software without necessarily invoking host software. Furthermore, embodiments of the invention enable more efficient delivery of interrupts to guest software by alleviating the need for host software to be invoked in the delivery process.

Abstract: A method for application managed CPU context switching. The method includes determining whether state data of a CPU is valid for a process. The determining is performed by the process itself. If the state data of the CPU is not valid for the process, the process accesses functional hardware of the CPU to load new state data into the CPU. The process then continues to execute on the CPU using the new state data. If a context switch occurs, the existing state data of the CPU is invalidated. The state data of the CPU can be invalidated by an operating system without storing the state data in main memory.

Abstract: The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the parallel subword compare operations can be stored at that bit position within the respective subword location of a result register. Alternatively, for a shifting-type instruction, pre-existing contents of a result register can be shifted one bit toward greater significance while the results are of the present operation are stored in the least-significant bits of respective result-register subword locations. This approach provides the results of multiple parallel subword compare instructions to be combined with relatively few instructions and reduces the maximum lateral movement of information—both of which can enhance performance.

Abstract: The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the parallel subword compare operations can be stored at that bit position within the respective subword location of a result register. Alternatively, for a shifting-type instruction, pre-existing contents of a result register can be shifted one bit toward greater significance while the results are of the present operation are stored in the least-significant bits of respective result-register subword locations. This approach provides the results of multiple parallel subword compare instructions to be combined with relatively few instructions and reduces the maximum lateral movement of information—both of which can enhance performance.

Abstract: Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an “Index” register. A direct variable Mux instruction can specify the table register and the index register as arguments, along with a result register. The instruction writes at least some of the data from the table register into the result register as specified in the index register. If the entire table cannot fit within a single register, entries can be divided between two or more table registers. An indirect variable Mux instruction can specify both a table-register-select register and a subword-location-select register. Both the direct and indirect Mux instructions can be used with entry data that is divided in accordance with significance between registers. In that case, plural Mux instructions are used with UnPack instructions that concatenate portions of the table entries.