Abstract: Hold time methods, systems, and computer program products are implemented to ensure that storage elements in a circuit have sufficient hold times without detrimentally affecting cycle times for other paths in the circuit. Electric circuits are designed by determining which storage elements have hold-time deficiencies, and by inserting an appropriate time delay element in a selected path preceding the storage element, or at a source or destination storage element, without exceeding a predetermined cycle time in a second path that overlaps the first path, for at least one storage element in an electrical circuit. The invention simulates insertion of the time delay element before or after a logic element that precedes a storage element that has a hold-time deficiency.

Abstract: An integrated circuit having a normal mode for operating under normal operating conditions and a debug mode for operating to test and debug the integrated circuit. The integrated circuit includes a plurality of output pins that carry a first plurality of signals in the normal mode and carry a second plurality of signals in the debug mode. In one embodiment, the integrated circuit embodies a microprocessor. The microprocessor may include logic circuitry for enabling the second plurality of signals to be output from a multiplexer to the output pins in response to a predetermined event, such as a hit in an associated memory unit.

Abstract: A pipeline control system for implementing a virtual architecture having a complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These operations, each having an associated tag, are issued to the functional units. Address processing unit computes addresses of the instructions and operands, performs segment relocation, and manages the processor's memory. Operations are executed by the units in a manner that is generally independent of operation processing by the other units. The units report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order.

Abstract: A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

Abstract: A pipeline control system for implementing a virtual architecture having a complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These operations, each having an associated tag, are issued to the functional units. Address processing unit computes addresses of the instructions and operands, performs segment relocation, and manages the processor's memory. Operations are executed by the units in a manner that is generally independent of operation processing by the other units. The units report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order.

Abstract: A pipeline control system for implementing a virtual architecture having complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These operations, each having an associated tag, are issued to the functional units. Address processing unit computes addresses of the instructions and operands, performs segment relocation, and manages the processor's memory. Operations are executed by the units in a manner that is generally independent of operation processing by the other units. The units report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order.

Abstract: A method and apparatus for improving the performance of pipelined computer processors having fast clock speeds and processing cycles for performing signed and unsigned load operations to memory. A load instruction includes signed and unsigned variants. Signed load operations include accessing signed load data from memory, aligning and sign extending the value of the accessed data. The present invention provides two different schemes for scheduling the processor's pipelines to handle accessing signed and unsigned data from memory. The two schemes include a data dependent scheme that accesses data from memory where the sign of a load data is not known until the data has been accessed from memory, and an opcode dependent scheme when the sign value of data being accessed is known prior to accessing memory. In the data dependent scheme, the processor is scheduled to process a signed LOAD in two cycles if the load data is negative, and one cycle if the data is positive.

Abstract: A central processing unit is connected to an external memory including system memory and an external cache. The central processing unit includes a First-In-First-Out (FIFO) load buffer configured to generate an access to the external memory in response to a data prefetch command. The access to external memory has an associated data load latency period as data is moved from the system memory into the external cache. Instead of requiring the access to external memory to be completed before another FIFO load buffer address is processed, as is typically required in a FIFO load buffer configuration, the FIFO load buffer responds to the data prefetch command by processing additional stored addresses during the data load latency period.

Abstract: A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

Abstract: A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

Abstract: A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.