Patents by Inventor Dale R. Jurich

Dale R. Jurich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8788792
    Abstract: A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: July 22, 2014
    Assignee: ATI Technologies ULC
    Inventors: John S. Yates, Jr., Matthew F. Storch, Sandeep Nijhawan, Dale R. Jurich, Korbin S. Van Dyke
  • Publication number: 20120144167
    Abstract: A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.
    Type: Application
    Filed: February 13, 2012
    Publication date: June 7, 2012
    Applicant: ATI Technologies ULC
    Inventors: John S. Yates, JR., Matthew F. Storch, Sandeep Nijhawan, Dale R. Jurich, Korbin S. Van Dyke
  • Patent number: 8127121
    Abstract: Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: February 28, 2012
    Assignee: ATI Technologies ULC
    Inventors: John S. Yates, Jr., Matthew F. Storch, Sandeep Nijhawan, Dale R. Jurich, Korbin S. Van Dyke
  • Publication number: 20080216073
    Abstract: Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler.
    Type: Application
    Filed: September 25, 2007
    Publication date: September 4, 2008
    Inventors: John S. Yates, Matthew F. Storch, Sandeep Nijhawan, Dale R. Jurich, Korbin S. Van Dyke
  • Patent number: 7275246
    Abstract: Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: September 25, 2007
    Assignee: ATI International SRL
    Inventors: John S. Yates, Jr., Sandeep Nijhawan, Matthew F. Storch, Dale R. Jurich
  • Patent number: 7065633
    Abstract: A computer concurrently executes a first operating system coded in a RISC instruction set and a second operating system coded in a CISC instruction set. When an exception is raised while executing a program coded in the RISC instruction set, an execution thread may be initiated under the CISC operating system. The exception may be delivered to the initiated thread for handling by the CISC operating system.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: June 20, 2006
    Assignee: ATI International SRL
    Inventors: John S. Yates, Jr., Matthew F. Storch, Sandeep Nijhawan, Dale R. Jurich, Korbin S. Van Dyke