Patents by Inventor Dalong Zhao
Dalong Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916338Abstract: An electrical connector assembly includes a pair of electrical connectors for electrically connecting to one another to close an electric circuit. The assembly further includes a connection indicator attached to one or more of the electrical connectors. The connection indicator generates a feedback, in response to the electrical connectors being one of connected to one another and disconnected from one another. The connection indicator is separate from the electric circuit, and the feedback is at least one of a radio frequency signal (RF signal), an electronic signal, a visible light, and an acoustic signal.Type: GrantFiled: July 23, 2021Date of Patent: February 27, 2024Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Xiang Zhao, Dalong Gao, Jinglin Li
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Patent number: 10217838Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: April 26, 2018Date of Patent: February 26, 2019Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Publication number: 20180261683Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.Type: ApplicationFiled: April 26, 2018Publication date: September 13, 2018Applicant: Mie Fujitsu Semiconductor LimitedInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 10014387Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: February 18, 2016Date of Patent: July 3, 2018Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 9991300Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.Type: GrantFiled: July 25, 2017Date of Patent: June 5, 2018Assignee: MIE Fujitsu Semiconductor LimitedInventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson
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Publication number: 20170323916Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.Type: ApplicationFiled: July 25, 2017Publication date: November 9, 2017Inventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson
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Patent number: 9812550Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.Type: GrantFiled: January 30, 2017Date of Patent: November 7, 2017Assignee: Mie Fujitsu Semiconductor LimitedInventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Patent number: 9793172Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.Type: GrantFiled: October 20, 2016Date of Patent: October 17, 2017Assignee: Mie Fujitsu Semiconductor LimitedInventors: Lance Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
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Patent number: 9786703Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.Type: GrantFiled: October 4, 2016Date of Patent: October 10, 2017Assignee: Mie Fujitsu Semiconductor LimitedInventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson
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Publication number: 20170141209Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.Type: ApplicationFiled: January 30, 2017Publication date: May 18, 2017Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
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Publication number: 20170040225Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.Type: ApplicationFiled: October 20, 2016Publication date: February 9, 2017Inventors: Lance Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
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Publication number: 20170025457Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.Type: ApplicationFiled: October 4, 2016Publication date: January 26, 2017Inventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson
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Patent number: 9514940Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.Type: GrantFiled: January 20, 2015Date of Patent: December 6, 2016Assignee: Mie Fujitsu Semiconductor LimitedInventors: Lance S. Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
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Patent number: 9478571Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.Type: GrantFiled: May 23, 2014Date of Patent: October 25, 2016Assignee: Mie Fujitsu Semiconductor LimitedInventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson
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Publication number: 20160307907Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.Type: ApplicationFiled: June 3, 2016Publication date: October 20, 2016Inventors: Scott E. Thompson, Thomas Hoffmann, Lance Scudder, Urupattur C. Sridharan, Dalong Zhao, Pushkar Ranade, Michael Duane, Paul Gregory
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Publication number: 20160268133Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.Type: ApplicationFiled: January 20, 2015Publication date: September 15, 2016Inventors: Lance S. Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
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Patent number: 9391076Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.Type: GrantFiled: December 18, 2014Date of Patent: July 12, 2016Assignee: Mie Fujitsu Semiconductor LimitedInventors: Scott E. Thompson, Thomas Hoffmann, Lance Scudder, Urupattur C. Sridharan, Dalong Zhao, Pushkar Ranade, Michael Duane, Paul Gregory
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Patent number: 9385047Abstract: Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.Type: GrantFiled: June 23, 2015Date of Patent: July 5, 2016Assignee: Mie Fujitsu Semiconductor LimitedInventors: Dalong Zhao, Pushkar Ranade, Bruce McWilliams
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Patent number: 9368624Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.Type: GrantFiled: July 24, 2015Date of Patent: June 14, 2016Assignee: Mie Fujitsu Semiconductor LimitedInventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
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Publication number: 20160163823Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.Type: ApplicationFiled: February 18, 2016Publication date: June 9, 2016Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann