Abstract: A message limit value to be used in enqueuing one or more messages on a queue of a device of the computing environment is obtained. The message limit value indicates whether an extended maximum message length is supported by the device. The extended maximum message length is different from a default maximum message length supported by the device. Based on determining that the extended maximum message length is supported and that the obtained message limit value has a defined relationship with a select value, at least one message of an extended length is enqueued on the queue of the device.

Abstract: A method, computer program product, and computer system are provided for supporting lossless transitions between interruption and polling mode of a resource. In response to a state variable setting or a timed trigger, launching a task to process replies for a resource. The task processes each ready reply for each resource. A timed trigger is established to relaunch the task based on the task executing in polling mode. The task is exited.

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Abstract: Dynamic relocation of virtual machines among hypervisors in a relocation domain is provided. A hypervisor is initialized in a subdomain of the relocation domain. A record of architecture characteristics is retrieved for each hypervisor in the relocation domain. A new canonical architectural description (ARD) is created for each subdomain in the relocation domain. An effective adapter characteristic representation is created for each virtual machine defined to the hypervisor. The record of architecture characteristics for each hypervisor in the relocation domain is updated.

Abstract: A message limit value to be used in enqueuing one or more messages on a queue of a device of the computing environment is obtained. The message limit value indicates whether an extended maximum message length is supported by the device. The extended maximum message length is different from a default maximum message length supported by the device. Based on determining that the extended maximum message length is supported and that the obtained message limit value has a defined relationship with a select value, at least one message of an extended length is enqueued on the queue of the device.

Abstract: Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.

Abstract: An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.

Abstract: Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.

Abstract: Dynamic relocation of virtual machines among hypervisors in a relocation domain is provided. A hypervisor is initialized in a subdomain of the relocation domain. A record of architecture characteristics is retrieved for each hypervisor in the relocation domain. A new canonical architectural description (ARD) is created for each subdomain in the relocation domain. An effective adapter characteristic representation is created for each virtual machine defined to the hypervisor. The record of architecture characteristics for each hypervisor in the relocation domain is updated.

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Abstract: Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.

Abstract: Aliasing errors, occasioned by including extra or missing bits, wrong addressing mode, or wrong address context, are detected by providing a storage configuration including gaps in valid addresses. An exception is thrown responsive to an address reference to a gap. Gaps are configured at complementary address ranges to facilitate detection of aliasing errors.

Abstract: Mapping of address space by providing real storage including first and second address spaces. The second address space is smaller than and contained within the first address space. Provided within virtual storage is a system execution space. Providing within the system execution space is a system execution area having a size equal to or less than the second address space. The system execution area includes a control program having a first portion capable of addressing the first address space and the system execution space, a second portion constrained to address only the second address space and the system execution area, and at least one alias page. Responsive to a control program request for a first page in the virtual storage, a first frame is assigned in real storage corresponding to the page. Responsive to a request from the second portion of the control program for the first page, allocating an alias page in the system execution area, the alias page backed by the first frame.

Abstract: Processing within a computing environment that supports pageable guests is facilitated. Processing is facilitated in many ways, including, but not limited to, associating guest and host state information with guest blocks of storage; maintaining the state information in control blocks in host memory; enabling the changing of states; and using the state information in management decisions. In one particular example, the guest state includes an indication of usefulness and importance of memory contents to the guest, and the host state reflects the ease of access to memory contents. The host and guest state information is used in managing memory of the host and/or guests.

Abstract: Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.

Abstract: The updating of components of storage keys is managed. A control program indicates whether the updating of selected components of a storage key can be bypassed. If the updating of the selected components can be bypassed, then depending on the circumstances, an update of the storage key may not need to be performed, saving on quiesce operations. The likelihood that the updating of a storage key can be bypassed is enhanced by selecting a block of storage, along with its associated storage key, from a designated queue or designated region of a queue.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent intervention of a host of the environment. The functions include a resolve host page function; a pin function; and unpin functions.