Abstract: Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.

Abstract: Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.

Abstract: The resistor segments may be placed in a spatial region of an integrated circuit. Junctions formed between the resistor segments and conductors may be placed at locations such that each junction has a paired counterpart of the same type that is spaced to form respective same junction type centroids (i.e., geometric centers). The different type centroids may be substantially coincident, meaning that the centroids substantially overlap. In this manner, junction voltages (or offset voltages) generated by one pair of junctions may cancel out the junction voltages generated by another pair of junctions in the resistor circuit.

Abstract: A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said seco

Abstract: A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said seco

Abstract: A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first

Abstract: A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first

Abstract: A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.

Abstract: A capacitive sensor including a housing having a hermetically sealed cavity, a plate in the cavity, a diaphragm forming a part of the cavity and spaced from the plate, a conductive layer on the first diaphragm, and a second conductive layer on the plate, the first and second conductive layers being the electrodes of a capacitor whose capacitance varies with the position of the diaphragm relative to the plate.

Abstract: An operational amplifier having two differential input stages. A first one of the stages comprises a pair of first input transistors and another one of such stages comprises a pair of second input transistors. The second input transistors are complementary in type to the first input transistors. A comparator is fed by a sense signal and a reference signal, such sense signal being related to at least one of a non-inverting and an inverting input signal fed to the operational amplifier. The comparator produces a control signal in accordance with a difference between the sense signal and the reference signal. A switching network is responsive to the control signal and couples an output of either the first one of the stages or the second one of the stages to an output of the operational amplifier selectively in accordance with the control signal.

Abstract: A method and circuit for providing a reference voltage to a charge balance circuit. The method includes transferring charge corresponding to VBE and charge corresponding to &Dgr;VBE to a summing node of the charge balance circuit, where VBE is a voltage produced across a p-n junction and where &Dgr;VBE is a difference between two VBE voltages. With such method, instead of forming a bandgap reference circuit which produces a bandgap reference voltage and applying such voltage to the reference sampling and charge transfer circuit, charge corresponding to VBE and charge corresponding to &Dgr;VBE are transferred to the input summing node of the modulator in correct proportion and with a polarity corresponding to the modulator output.

Abstract: An analog to digital conversion system having a plurality of analog to digital converters (ADCs). Each one of such ADCs is configured to convert a corresponding one of a plurality of analog signals into a corresponding sequence of digital words. The ADCs have different degrees of conversion performance. A source of the pulses is included. Each one of the ADCs is configured to provide a corresponding one of the sequences of digital words in response to the pulses. Each one of the digital words in each of the sequences is provided at substantially the same time. A controller is provided for interrupting and/or changing the configuration of one or more of the ADCs. The controller provides the interrupt and/or change in configuration with a priority to one of the ADCs over the other one of the ADCs.

Abstract: A digital filtering system is fed by input signal and produces an output signal from either a relatively low bandwidth filter or a relatively wide bandwidth filter selectively in accordance with the time rate of change in the input signal. The output signal is produced by the relatively low bandwidth filter when the input signal is slowly varying and the output signal is produced by the relatively wide bandwidth filter when the input signal changes rapidly, after which the output is produced from the relatively low bandwidth filter when the input signal reverts to its more slowly varying characteristics.

Abstract: An invalid reference detection circuit formed on a semiconductor chip having: reference input terminals adapted for coupling to a reference source external to the chip; a local reference source; and comparison circuit. The comparison circuit is responsive to the local reference source and a condition at the reference input terminals to detect an invalid condition at the reference input terminals and to produce an output signal indicative of the detected invalid condition. The invalid condition at the reference input terminals may be an open circuit condition at at least one of the reference input terminals, a condition when the voltage across the reference input terminals is below a predetermined minimum voltage level, a condition when the voltage across the reference input terminals is above a predetermined maximum voltage level, and/or a short circuit condition. An analog/digital conversion system is formed on a semiconductor chip together with the invalid reference detection circuit.

Abstract: A digital filtering system is fed by input signal and produces an output signal from either a relatively low bandwidth filter or a relatively wide bandwidth filter selectively in accordance with the time rate of change in the input signal. The output signal is produced by the relatively low bandwidth filter when the input signal is slowly varying and the output signal is produced by the relatively wide bandwidth filter when the input signal changes rapidly, after which the output is produced from the relatively low bandwidth filter when the input signal reverts to its more slowly varying characteristics.

Abstract: A method, and apparatus, for calibrating a delta sigma modulator. The delta sigma modulator includes an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor. During the calibration mode, a feedback signal sampling section samples a feedback signal and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor in each modulator cycle and an input signal section samples a calibration signal and transfers packets of charge corresponding to a portion of the calibration signal to the integrating capacitor in each modulator cycle. With such an arrangement, some charge is transferred to the integration capacitor in each modulator cycle thus reducing idle-tones.

Abstract: An analog to digital conversion system wherein a first chopper is responsive to a chop signal having a period T for passing an analog signal to an output with non-reversed polarity during a first portion of the period T and with reversed polarity during a second portion of the period T. An analog to digital converter produces a first set of at least one digital word corresponding to the analog signal with non-reversed polarity and an offset voltage and produces a second set of at least one digital word corresponding to the analog signal with reversed polarity and the offset voltage. A second chopper is responsive to the chop signal for passing to an output of the second chopper one of the produced first and second sets with non-reversed polarity, and passing to the output of the second chopper the other one of produced first and second sets with reversed polarity.

Abstract: A switched-capacitor DAC system includes an integrator circuit including an op amp having an input lead, an output lead and an integrator capacitor connected between the input lead and the output lead. A sampling switch is operable to connect an input capacitor to be charged by an input voltage during at least one of first and second non-overlapping time intervals, wherein the first time interval is subdivided into first and second non-overlapping sub-intervals and the second time interval is subdivided into third and fourth non-overlapping sub-intervals. A transferring switch is operable to connect the input capacitor to transfer charge from the input capacitor to transfer charge from the input capacitor to the integrator capacitor during at least one of the first and third sub-intervals. A discharging switch is operable to connect the input capacitor to a discharge node during at least one of the second and fourth sub-intervals.

Abstract: A switched-capacitor auto-zero integrator includes and integrator circuit and a correction circuit. The integrator circuit may be any circuit including an operational amplifier having an input line and an output line, an input capacitor coupled to be charged by an Input voltage, an integrating capacitor coupled to the output line, and at least one integrating switch operable during an integrating time interval to connect the input capacitor to the integrating capacitor such that the integrating capacitor is charged to compensate for charge of the input capacitor. The correction circuit includes an offset capacitor coupled to the input line and at least one correction switch operable in an auto-zero sub-interval: and a correction sub-interval.

Abstract: A delta sigma modulator provides dual phase sampling of analog input and/or a reference voltage. This dual phase sampling may be realized using a switched capacitor circuit having dual legs with a capacitor on each such leg. The dual phase sampling of the reference voltage poses a complication that mandates the necessity of providing a compensation signal. The delta sigma modulator is provided with appropriate circuitry to provide a compensation signal that compensates for the reduced signal level due to the dual sampling. In particular, the delta sigma modulator compensates for the reduced level of the output from an integrating amplifier circuit due to the timing necessary to implement the dual sampling approach.