Abstract: An application-specific integrated circuit (ASIC) with a CPU module and a memory module connected to the CPU. The memory has a size selected from a set of alternative memory sizes. The CPU has a memory interface device having an output connected to the memory, and includes a memory test device connected to the memory. The memory test device has a size selector input that receives a memory size code, so that the memory test device is operable to test a memory module of any of the alternative memory sizes in response to alternative memory size codes received on the size selector input. The memory may be RAM or ROM, and the size codes may correspond to address size data stored in the memory test device.

Abstract: A timing circuit that utilizes the delay inherent in a clock tree to achieve a desired timing relationship between control or clock signals. The timing circuit is particularly applicable to high speed environments and to asynchronous logic, though it is also applicable to lower speed environments and synchronous logic. A method producing the desired control or clock signals is also disclosed.