Abstract: A drop generator including a fluid channel substructure having a pressure chamber and an inlet formed therein, a diaphragm layer overlying the fluid channel substructure, a transducer substructure attached to the diaphragm layer, and an ink feed aperture formed in the diaphragm layer.

Abstract: A printing system includes a print head to deliver ink to an image receptor and at least one ink reservoir to deliver ink to the print head. Driving circuitry provides signals to the print head to control delivery of the ink and a flexible circuit interposed between the print head and the ink reservoirs connects the driving circuitry to the print head. The flexible circuit may include a heater to provide heat to the ink reservoirs. Alternatively, the flexible circuit may be replaced with a rigid substrate having a heater within its layers.

Abstract: A printing system includes a print head to deliver ink to an image receptor and at least one ink reservoir to deliver ink to the print head. Driving circuitry provides signals to the print head to control delivery of the ink and a flexible circuit interposed between the print head and the ink reservoirs connects the driving circuitry to the print head. The flexible circuit may include a heater to provide heat to the ink reservoirs. Alternatively, the flexible circuit may be replaced with a rigid substrate having a heater within its layers.

Abstract: A drop generator including a fluid channel substructure having a pressure chamber and an inlet formed therein, a diaphragm layer overlying the fluid channel substructure, a transducer substructure attached to the diaphragm layer, and an ink feed aperture formed in the diaphragm layer.

Abstract: Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within extremely tight time tolerances of each other. The delays associated with each component, electrical or optical connection, cable or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence from the master clock source to the final chip delivery point is logged and summed. Components capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components, or in substantially all optical configurations.

Abstract: The present invention includes methods and apparatus for creating a packaging architecture for a highly parallel multiprocessor system. The packaging architecture of the present invention can provide for distribution of power, cooling and interconnections at all levels of components in a highly parallel multiprocessor system, while maximizing the number of circuits per unit time within certain operational constraints of such a multiprocessor system.