Abstract: A circuit system includes an analog-to-digital converter circuit, a digital-to-analog converter circuit coupled to the analog-to-digital converter circuit, and a variable latency circuit coupled to a data path that includes the digital-to-analog converter circuit. The variable latency circuit generates a deterministic latency in an output signal that is based on a measured latency of the data path.

Abstract: A circuit system includes an analog-to-digital converter circuit, a digital-to-analog converter circuit coupled to the analog-to-digital converter circuit, and a variable latency circuit coupled to a data path that includes the digital-to-analog converter circuit. The variable latency circuit generates a deterministic latency in an output signal that is based on a measured latency of the data path.

Abstract: A systolic array implemented in circuitry of an integrated circuit, includes a processing element array having processing elements arranged in a vertical direction and a horizontal direction, first loaders communicatively coupled to the processing element array to load samples Am,n from at least one external memory to the processing element array, and second loaders communicatively coupled to the processing element array to load samples Bk,l from the at least one external memory to the processing element array. Each row of the samples Am,n is loaded one row at a time to a single processing element along the horizontal direction, and each row of the samples Bk,l is loaded one row at a time to a single processing element along the vertical direction, wherein pairing between the samples Am,n and Bk,l in the horizontal direction and the vertical direction enables data reuse to reduce bandwidth usage of the external memory.

Abstract: Systems, methods, and machine-readable media are provided to perform adaptive beamforming using beamformer weights that compensate for undesirable signal path delays of a phased array. Such a system may include an array of elements that receive respective signals, analog-to-digital conversion circuitry to digitize the signals, and adaptive beamforming circuitry that performs beamforming using the digitized signals. The digitized signals used by the adaptive beamforming circuitry may not be aligned in time due to differences in analog delays between the array of elements and the analog-to-digital conversion circuitry. Even so, the adaptive beamforming circuitry may generate beamformer weights that compensate for the analog delays.

Abstract: A computing system may include a recursive circuit with a feedback path. The recursive circuit may be provided with an orthogonal transformation circuit configured to decompose a single input data stream into independent components that can then be processed by the recursive circuit. The recursive circuit may further be provided with an inverse orthogonal transformation circuit configured to recombine the independent components that have been processed by the recursive circuit into a single output data stream. Operated in this way, the throughput of the recursive system can be optimized such that the recursive circuit is capable of outputting samples at the maximum clock frequency of the underlying computing system.

Abstract: An array of antennas includes transmitter and receiver circuits. The transmitter includes a digital-to-analog converter (DAC), splitter and filter circuits, mixer circuits, and antennas. The DAC circuit converts a digital signal into an analog signal. The splitter and filter circuits separate frequencies of the analog signal into split signals. The mixer circuits multiply frequencies from the split signals by different frequencies of carrier signals to generate modulated signals that are converted by the antennas into radio frequency (RF) signals. The receiver includes antennas, mixer circuits, a summing circuit, and an analog-to-digital converter (ADC). The antennas in the receiver receive RF signals that are converted into electrical signals. The mixer circuits multiply frequencies from the electrical signals with different frequencies of carrier signals. The outputs of the mixer circuits are summed by the summing circuit to generate a summed signal that is converted to digital by the ADC.

Abstract: A systolic array implemented in circuitry of an integrated circuit, includes a processing element array having processing elements arranged in a vertical direction and a horizontal direction, first loaders communicatively coupled to the processing element array to load samples Am,n from at least one external memory to the processing element array, and second loaders communicatively coupled to the processing element array to load samples Bk,l from the at least one external memory to the processing element array. Each row of the samples Am,n is loaded one row at a time to a single processing element along the horizontal direction, and each row of the samples Bk,l is loaded one row at a time to a single processing element along the vertical direction, wherein pairing between the samples Am,n and Bk,l in the horizontal direction and the vertical direction enables data reuse to reduce bandwidth usage of the external memory.

Abstract: Techniques and mechanisms disclosed herein add dithering noise to a receiver to reduce harmonics.

Abstract: A signal monitoring system includes a splitter circuit, a single-bit channel circuit, a multi-bit channel circuit, and a frequency processor circuit. The splitter circuit splits a first analog signal into second and third analog signals. The single-bit channel circuit samples the second analog signal at a sampling rate that is greater than or equal to a Nyquist rate of the second analog signal to generate a first digital signal. The multi-bit channel circuit under-samples the third analog signal at a sampling rate that is less than a Nyquist rate of the third analog signal to generate second digital signals. The frequency processor circuit resolves a Nyquist zone ambiguity in the second digital signals using the first digital signal to generate an unambiguous output signal.

Abstract: Circuitry for interpolating a value based on a first plurality of samples from within a larger second plurality of samples includes storage for the second plurality of samples, including a plurality of sample memories corresponding in number to the first plurality of samples. Adjacent samples in the sample memories correspond to samples in the second plurality of samples that are separated by other samples numbering one less than that number. A first sample address into a first one of the sample memories is derived by dividing a floor of an index by the number. Respective circuitry for each respective other one of the sample memories derives a respective other sample address from the first sample address based on a remainder of dividing the floor of the index by the number. Shifting circuitry outputs selected samples in a second order under control of a value determined by the remainder.

Abstract: First delay mechanisms to delay a beam-detect signal by different lengths of time in synchronization with a first clock signal. The beam-detect signal is generated responsive to one or more beams being output towards a rotating polygonal mirror having facets and directed towards a sensor. One or more second delay mechanisms each correspond to one of the beams to delay a second clock signal, resulting in a beam-clock signal to align the beam over successive reflections by the facets. A mechanism determines a delay by which each second delay mechanism is to delay the second clock signal, based on the beam-detect signal as differently delayed by the first delay mechanisms.

Abstract: First delay mechanisms to delay a beam-detect signal by different lengths of time in synchronization with a first clock signal. The beam-detect signal is generated responsive to one or more beams being output towards a rotating polygonal mirror having facets and directed towards a sensor. One or more second delay mechanisms each correspond to one of the beams to delay a second clock signal, resulting in a beam-clock signal to align the beam over successive reflections by the facets. A mechanism determines a delay by which each second delay mechanism is to delay the second clock signal, based on the beam-detect signal as differently delayed by the first delay mechanisms.