Patents by Inventor Dan Skinner
Dan Skinner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11914530Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: GrantFiled: July 14, 2022Date of Patent: February 27, 2024Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Publication number: 20220350760Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: ApplicationFiled: July 14, 2022Publication date: November 3, 2022Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Patent number: 11403240Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: GrantFiled: October 7, 2016Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Publication number: 20170024337Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: ApplicationFiled: October 7, 2016Publication date: January 26, 2017Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Patent number: 9477636Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: GrantFiled: October 21, 2009Date of Patent: October 25, 2016Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Patent number: 9164698Abstract: Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.Type: GrantFiled: May 5, 2014Date of Patent: October 20, 2015Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, Dan Skinner, J. Thomas Pawlowski
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Patent number: 8930642Abstract: Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.Type: GrantFiled: August 20, 2012Date of Patent: January 6, 2015Assignee: Micron Technology, Inc.Inventors: Robert Walker, Dan Skinner
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Patent number: 8930643Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.Type: GrantFiled: June 9, 2014Date of Patent: January 6, 2015Assignee: Micron Technology, Inc.Inventors: Dan Skinner, J. Thomas Pawlowski
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Publication number: 20140289482Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.Type: ApplicationFiled: June 9, 2014Publication date: September 25, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Dan Skinner, J. Thomas Pawlowski
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Publication number: 20140244948Abstract: Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.Type: ApplicationFiled: May 5, 2014Publication date: August 28, 2014Applicant: Micron Technology, Inc.Inventors: Robert M. Walker, Dan Skinner, J. Thomas Pawlowski
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Patent number: 8769213Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.Type: GrantFiled: August 24, 2009Date of Patent: July 1, 2014Assignee: Micron Technology, Inc.Inventors: Dan Skinner, J. Thomas Pawlowski
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Patent number: 8719516Abstract: Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.Type: GrantFiled: October 21, 2009Date of Patent: May 6, 2014Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, Dan Skinner, J. Thomas Pawlowski
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Publication number: 20120314523Abstract: Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.Type: ApplicationFiled: August 20, 2012Publication date: December 13, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Robert Walker, Dan Skinner
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Patent number: 8250312Abstract: Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.Type: GrantFiled: April 29, 2009Date of Patent: August 21, 2012Assignee: Micron Technology, Inc.Inventors: Robert Walker, Dan Skinner
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Publication number: 20110093665Abstract: Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.Type: ApplicationFiled: October 21, 2009Publication date: April 21, 2011Applicant: Micron Technology, Inc.Inventors: Robert M. Walker, Dan Skinner, J. Thomas Pawlowski
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Publication number: 20110093662Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).Type: ApplicationFiled: October 21, 2009Publication date: April 21, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
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Publication number: 20110047311Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.Type: ApplicationFiled: August 24, 2009Publication date: February 24, 2011Inventors: Dan Skinner, J. Thomas Pawlowski
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Publication number: 20100281227Abstract: Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.Type: ApplicationFiled: April 29, 2009Publication date: November 4, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Robert Walker, Dan Skinner