Abstract: A microprocessor with a multiplexer having its output coupled to the input of the instruction register for storing instructions to be executed and applying the bits of the instruction as the input signals to a mapping PLA. The inputs of the multiplexer are the information bus coupled to external pins to receive instructions either from external memory or from an external console, and the output of the ALU. The path from the output of the ALU to the input of the instruction register allows better self testing of the processor by iteself and self-generation of input/output instructions. This structure simplifies the processor by allowing console requests, instructions from memory and self generated instructions all to be stored in the same register, i.e., the instruction register, thereby eliminating the need for separate registers for each type of instruction.

Abstract: A microprocessor comprising: an address data path; an arithmetic logic unit data path, said data paths being capable of simultaneous operation; an information bus; a shared bus register; a shared input multiplexing apparatus for selectively transferring address and data information from said information bus and data information from said arithmetic logic unit data path to said shared bus register; and a multiplexing apparatus for transferring information from said shared bus register to said arithmetic logic unit data path and to said information bus via said address data path whereby said shared bus register is selectively useable as a memory data register, a memory address register and a temporary or "scratch-pad" register during normal operation of the microprocessor; and further comprising; a programmable logic array containing a sequence of microinstructions and apparatus connected thereto for testing the operability of the microprocessor.

Abstract: A central processing unit (CPU) is utilized in combination with external memories and input/output devices to form a Microcomputer System. The CPU is a 16-bit fixed word length processor monolithically integrated onto a single semiconductor chip which uses two's complement arithmetic for computations. The CPU includes an arithmetic logic unit (ALU), accumulators, data path multiplexers, program counter means, and programmable logic arrays to control operation of the processor.The processor of this invention is capable of using a homogeneous memory, wherein instructions and data are both stored in the same memory. In the disclosed embodiment, 15 of the 16-bits are used for addressing the memory. Thus, the processor is capable of directly addressing 32,768 16-bit words in the memory.An external 16-bit bus is used to interconnect the external memory and input/output devices with the CPU.