Patents by Inventor Dana Moore

Dana Moore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060231328
    Abstract: A low frequency exponential/hyperbolic hybrid folded horn enclosure intended for use in proximity with at least one planar surface, such as a floor, ceiling, or wall, with access to the horn throat from the top of the enclosure. The horn is bifurcated at the throat and folds horizontally around a central trapezoid-shaped vertical back chamber which is reflex ported for enhanced low frequency response below the frequency cutoff of the horn. The back chamber outer sides define part of the horn channel, resulting in a relatively simple structure with a small footprint and no void internal space.
    Type: Application
    Filed: April 16, 2005
    Publication date: October 19, 2006
    Inventor: Dana Moore
  • Publication number: 20050276431
    Abstract: A low frequency exponential horn enclosure intended for corner use with access to the horn throat and entire volume of the back chamber from the top of the enclosure, allowing operation as either a front or back loaded horn. The horn is bifurcated at the throat and folds horizontally around a central triangle-shaped columnar back chamber, the sides of which form part of the horn channel, forming a simple structure with little void space.
    Type: Application
    Filed: June 9, 2004
    Publication date: December 15, 2005
    Inventor: Dana Moore
  • Patent number: 4323965
    Abstract: A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which selects the row of chips to be accessed within one of the pair of memory units. Address decode circuits include gating circuits which couple to both module units. The gating circuits are interconnected so that the decoding of the least significant address bits results in the generation of a pair of row address strobe signals. These signals enable simultaneously the rows of RAM chips for access within both module units for read out of information to a multiword bus eliminating any delay in address incrementing.
    Type: Grant
    Filed: January 8, 1980
    Date of Patent: April 6, 1982
    Assignee: Honeywell Information Systems Inc.
    Inventors: Robert B. Johnson, Chester M. Nibby, Jr., Dana Moore