Abstract: The present invention relates to a field of control of nitrogen oxide pollution, and involves a high-efficient catalyst for denitration at low temperature and preparation method thereof, which comprises the steps: (1) preparing aqueous solution of cerium nitrate; (2) soaking mesoporous silica materials SBA-15 with aqueous solution from step (1), after stirring, filtrating, washing and drying; (3) calcining materials from step (2) to obtain evenly dispersed CeO2-SBA-15 materials; (4) preparing ethanol solution of manganese nitrate; (5) soaking CeO2-SBA-15 materials from step (3) with ethanol solution of manganese nitrate from step (4) and volatilizing ethanol, washing and drying; (6) calcining materials from step (5) to obtain evenly distributed MnxOy/CeO2-SBA-15 catalyst for denitration; The preparation method has simple process with lower cost, and the obtained MnxOy/CeO2-SBA-15 catalyst has uniform and ordered pores, large specific area, narrow pore size distribution, well dispersity of catalytic components

Abstract: Mesoporous ternary composite materials and a corresponding preparation method are described herein. The method includes the following steps: (1) adding hydrochloric acid and acetic acid into an ethanol solution to prepare a dissolving system; (2) adding a surfactant into the dissolving system and fully stirring for dissolution; (3) adding copper nitrate, manganese nitrate solution and tetrabutyl titanate into the mixed liquid obtained from step (2) and evenly stirring ; (4) transferring the mixture obtained from step (3) into petri dishes and obtaining transparent films after drying; and (5) calcinating the transparent films to obtain mesoporous ternary composite materials. The materials prepared are ordered mesoporous materials with high specific surface areas and high dispersion degree of every component.

Abstract: The invention discloses a lower-temperature sealing glass frit and a method for preparing a composite filler in the glass frit. The lower-temperature sealing glass frit includes a glass powder and a negative thermal expansion composite filler with an adjustable thermal expansion coefficient. The thermal expansion coefficient of the low-temperature sealing glass frit into which the composite material and the glass powder is mixed can be adjustable so that the thermal expansion coefficient of the low-temperature sealing glass frit can match the thermal expansion coefficient of glass substrates packaging an OLED device to thereby improve the yield of the packaged OLED device.

Abstract: The invention discloses a lower-temperature sealing glass frit and a method for preparing a composite filler in the glass frit. The lower-temperature sealing glass frit includes a glass powder and a negative thermal expansion composite filler with an adjustable thermal expansion coefficient. The thermal expansion coefficient of the low-temperature sealing glass frit into which the composite material and the glass powder is mixed can be adjustable so that the thermal expansion coefficient of the low-temperature sealing glass frit can match the thermal expansion coefficient of glass substrates packaging an OLED device to thereby improve the yield of the packaged OLED device.

Abstract: The invention provides a method and a device for determining a festival best-selling commodity, which is capable of filtering a festival best-selling commodity more accurately from a large number of commodities. The method comprises the following steps of: for each commodity in a plurality of commodities, based on a comparison of sales of the commodity during a predetermined festival to sales in a predetermined time period during which the festival lasts, calculating a best-selling degree of the commodity during the festival; and determining a commodity with a higher best-selling degree as the festival best-selling commodity.

Abstract: To improve upon efficiency of a transmitter's power amplifier during low power operation, a switching system is used to selectively switch between different (e.g., normal and reduced) power supplies. Suitable hardware/software in the form of circuitry, logic gates, and/or code functions to process, amplify, and transmit an input RF signal and selectively switch IN/OUT a plurality of supply voltages using control logic.

Abstract: To improve upon efficiency of a transmitter's power amplifier during low power operation, a switching system is used to selectively switch between different (e.g., normal and reduced) power supplies. Suitable hardware/software in the form of circuitry, logic gates, and/or code functions to process, amplify, and transmit an input RF signal and selectively switch IN/OUT a plurality of supply voltages using control logic.

Abstract: Certain aspects of a method and system for mitigating effects of pulling in multiple phase locked loops in multi-standard systems may include selecting an input frequency range of operation at a voltage controlled oscillator based on a particular wireless band of operation in a system that handles a first wireless communication protocol and a second wireless communication protocol. An image rejection mixer may be enabled to generate an output signal for the particular wireless band of operation based on mixing a plurality of received signals within a selected frequency range. An in-phase (I) component and a quadrature (Q) component of the generated output signal may be generated by utilizing a RC-CR quadrature network.

Abstract: A method for drilling a well along a planned trajectory includes: receiving downhole data from a steerable drilling tool; processing the downhole data and creating a downlink path, the downlink path being recognizable by the steerable drilling tool; and controlling the trajectory of the steerable drilling tool based on the downlink path.

Abstract: In one embodiment, a method comprising during a first calibration instance, converting at a first transconductance stage a first output voltage from a power amplifier of a transceiver to a first set of current signals; and during a second calibration instance not overlapping the first calibration instance, converting at a second transconductance stage a second output voltage from the power amplifier to a second set of current signals.

Abstract: A down conversion module includes a mixer operable to down convert an amplified receive signal from a low noise amplifier, based on a local oscillation, to produce a mixer output signal. A mixer load section is operable to produce a down converted signal from mixer output at an output of the mixer load section. A direct current (DC) offset cancellation module is operable to measure a DC offset at the output of the mixer load section, to generate cancellation currents and to combine the cancellation currents with the mixer output signal to provide DC offset cancellation.

Abstract: A low noise amplifier includes a programmable input stage, having a first gain that is programmable based on a first control signal. A programmable cascode stage, has a second gain that is programmable based on a second control signal. A programmable resistor stage controls the quality of a resonant tank circuit, based on a third control signal.

Abstract: Aspects of a method and system for precise current matching in deep sub-micron technology may include adjusting a current mirror to compensate for MOSFET gate leakage currents by using feedback circuits. The feedback circuits may be implemented from active components to create active feedback circuits. If the reference current to be mirrored is noisy, a smoothing effect may be achieved by introducing a low-pass filter coupled to the current mirror design. The active feedback may comprise amplifiers, which may comprise one or more amplifier stages. The amplifier may amplify either a bias voltage error or a bias current error. Furthermore, a transimpedance amplifier may be utilized in the feedback loop. The output bias current of the current mirror may be stabilized dynamically during adjusting. Multiple current sources may be utilized in the current mirrors.

Abstract: Aspects of a method and system for use of true single phase clock (TSPC) logic for a high-speed multi-modulus divider in a phase locked loop (PLL) are provided. A fractional-N PLL synthesizer may comprise a divider that generates a divider signal from a VCO output reference signal. The divider may comprise at least one divider stage that utilizes true single phase clock (TSCP) logic D flip-flops. The first divider stage may operate at substantially the same frequency as that of the VCO signal. The divider may also re-synchronize the VCO signal and the divider signal by using at least two re-synchronization stages that utilize a TSCP logic D flip-flop and a stage for adjusting duty-duty cycle of the divider signal. The TSCP logic D flip-flops circuitry may be integrated with a two-input NAND gate or a three-input NAND gate to speed up the operation of the divider.

Abstract: A method and apparatus in an integrated circuit radio transceiver are operable to apply a modified control signal to drive logic that includes a plurality of first devices having a first threshold voltage and a first gate oxide thickness that are both greater than a second threshold voltage and a second gate oxide thickness for a greater second plurality of devices within the integrated circuit radio transceiver. The transceiver therefore generates a first control signal having a first magnitude operable to drive logic that includes a plurality of devices having a second threshold voltage and applies the first control signal to a level shifter to produce the modified control signal.

Abstract: Certain aspects of a method and system for mitigating effects of pulling in multiple phase locked loops in multi-standard systems may include selecting an input frequency range of operation at a voltage controlled oscillator based on a particular wireless band of operation in a system that handles a first wireless communication protocol and a second wireless communication protocol. An image rejection mixer may be enabled to generate an output signal for the particular wireless band of operation based on mixing a plurality of received signals within a selected frequency range. An in-phase (I) component and a quadrature (Q) component of the generated output signal may be generated by utilizing a RC-CR quadrature network.

Abstract: Certain aspects of a method and system for mitigating effects of pulling in multiple phase locked loops in multi-standard systems may include selecting an input frequency range of operation at a voltage controlled oscillator based on a particular wireless band of operation in a system that handles a first wireless communication protocol and a second wireless communication protocol. An image rejection mixer may be enabled to generate an output signal for the particular wireless band of operation based on mixing a plurality of received signals within a selected frequency range. An in-phase (I) component and a quadrature (Q) component of the generated output signal may be generated by utilizing a RC-CR quadrature network.

Abstract: Aspects of a method and system for implementing a low power, high performance fractional-N PLL synthesizer are provided. The synthesizer comprises a reference generator/buffer, a charge pump, a divider, a VCO, a loop filter, and a phase-frequency detector (PFD). The reference generator/buffer may increase the frequency of the input reference signal to the PFD. The PFD may generate a single signal for controlling the charge pump utilizing the increased frequency input reference signal and a divider signal generated by the divider whose input frequency may be substantially the same as that of a VCO output signal. The single signal charges a charge up portion of the charge pump and a charge down portion is charged by a leakage current. The VCO signal may be generated based on a filtered output of the charge pump generated by the loop filter. The divider may utilize true single phase clock (TSPC) logic.

Abstract: Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.

Abstract: A method and apparatus in an integrated circuit radio transceiver are operable to apply a modified control signal to drive logic that includes a plurality of first devices having a first threshold voltage and a first gate oxide thickness that are both greater than a second threshold voltage and a second gate oxide thickness for a greater second plurality of devices within the integrated circuit radio transceiver. The transceiver therefore generates a first control signal having a first magnitude operable to drive logic that includes a plurality of devices having a second threshold voltage and applies the first control signal to a level shifter to produce the modified control signal.