Patents by Inventor Daniel B. Bergstrom
Daniel B. Bergstrom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11094587Abstract: In one embodiment, a conductive connector for a microelectronic component may be formed with a noble metal layer, acting as an adhesion/wetting layer, disposed between a barrier liner and a conductive fill material. In a further embodiment, the conductive connector may have a noble metal conductive fill material disposed directly on the barrier liner. The use of a noble metal as an adhesion/wetting layer or as a conductive fill material may improve gapfill and adhesion, which may result in the conductive connector being substantially free of voids, thereby improving the electrical performance of the conductive connector relative to conductive connectors without a noble metal as the adhesion/wetting layer or the conductive fill material.Type: GrantFiled: June 3, 2015Date of Patent: August 17, 2021Assignee: Intel CorporationInventors: Christopher J. Jezewski, Srijit Mukherjee, Daniel B. Bergstrom, Tejaswi K. Indukuri, Flavio Griggio, Ramanan V. Chebiam, James S. Clarke
-
Patent number: 11063151Abstract: Metal chemical vapor deposition approaches for fabricating wrap-around contacts, and semiconductor structures having wrap-around metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor feature above a substrate. A dielectric layer is over the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-flat topography. A metallic contact material is directly on the portion of the semiconductor feature. The metallic contact material is conformal with the non-flat topography of the portion of the semiconductor feature. The metallic contact material has a total atomic composition including 95% or greater of a single metal species.Type: GrantFiled: March 30, 2017Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Jeffrey S. Leib, Daniel B. Bergstrom, Christopher J. Wiegand
-
Patent number: 11018222Abstract: Disclosed herein are structures, methods, and assemblies related to metallization in integrated circuit (IC) structures. For example, in some embodiments, an IC structure may include a first nanowire in a metal region and a second nanowire in the metal region. A distance between the first nanowire and the second nanowire may be less than 5 nanometers, and the metal region may include tungsten between the first nanowire and the second nanowire.Type: GrantFiled: December 27, 2019Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Daniel B. O'Brien, Christopher J. Wiegand, Lukas M. Baumgartel, Oleg Golonzka, Dan S. Lavric, Daniel B. Bergstrom, Jeffrey S. Leib, Timothy Michael Duffy, Dax M. Crum
-
Patent number: 10804460Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.Type: GrantFiled: July 1, 2016Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Daniel G. Ouellette, Kevin P. O'Brien, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, Daniel B. Bergstrom, Justin S. Brockman, Oleg Golonzka, Tahir Ghani
-
Patent number: 10777421Abstract: Technologies for selectively etching oxide and nitride materials on a work piece are described. Such technologies include methods for etching a work piece with a remote plasma that is produced by igniting a plasma gas flow. Microelectronic devices including first and second fins that are laterally offset by a fin pitch to define a first field there between are also described. In embodiments the microelectronic devices include a conformal oxide layer and a conformal nitride layer on at least a portion of the first and second fins, where the conformal nitride layer is on at least a portion of the conformal oxide layer and a sacrificial oxide material is disposed within the first field.Type: GrantFiled: September 18, 2017Date of Patent: September 15, 2020Assignee: Intel CorporationInventors: Jason A. Farmer, Gopinath Trichy, Justin S. Sandford, Daniel B. Bergstrom
-
Patent number: 10651082Abstract: In an example, there is disclosed a chemical compound, including a transition metal, a post-transition metal, a metalloid, and a nonmetal. By way of non-limiting example, the post-transition metal may be aluminum. The transition metal is selected from the group consisting of tungsten, tantalum, hafnium, molybdenum, niobium, zirconium, vanadium, and titanium. The metalloid may be boron or silicon. The nonmetal may be carbon or nitrogen. The compound may be used, for example, as a barrier material in an integrated circuit.Type: GrantFiled: March 31, 2016Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Daniel J. Zierath, Jason A. Farmer, Daniel B. Bergstrom
-
Publication number: 20200066645Abstract: Embodiments of the invention include a microelectronic device that includes a substrate having a layer of dielectric material that includes a feature with a depression, a Tungsten containing barrier liner layer formed in the depression of the feature, and a Cobalt conductive layer deposited on the Tungsten containing barrier liner layer in the depression of the feature. The Tungsten containing barrier liner layer provides adhesion for the Cobalt conductive layer.Type: ApplicationFiled: September 30, 2016Publication date: February 27, 2020Applicant: Intel CorporationInventors: Jason A. FARMER, Jeffrey S. LEIB, Michael L. MCSWINEY, Harsono S. SIMKA, Daniel B. BERGSTROM
-
Publication number: 20190393336Abstract: Metal chemical vapor deposition approaches for fabricating wrap-around contacts, and semiconductor structures having wrap-around metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor feature above a substrate. A dielectric layer is over the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-flat topography. A metallic contact material is directly on the portion of the semiconductor feature. The metallic contact material is conformal with the non-flat topography of the portion of the semiconductor feature. The metallic contact material has a total atomic composition including 95% or greater of a single metal species.Type: ApplicationFiled: March 30, 2017Publication date: December 26, 2019Inventors: Jeffrey S. LEIB, Daniel B. BERGSTROM, Christopher J. WIEGAND
-
Publication number: 20190140166Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.Type: ApplicationFiled: July 1, 2016Publication date: May 9, 2019Inventors: MD Tofizur RAHMAN, Christopher J. WIEGAND, Brian MAERTZ, Daniel G. OUELLETTE, Kevin P. O'BRIEN, Kaan OGUZ, Brian S. DOYLE, Mark L. DOCZY, Daniel B. BERGSTROM, Justin S. BROCKMAN, Oleg GOLONZKA, Tahir GHANI
-
Publication number: 20190088538Abstract: In an example, there is disclosed a chemical compound, including a transition metal, a post-transition metal, a metalloid, and a nonmetal. By way of non-limiting example, the post-transition metal may be aluminum. The transition metal is selected from the group consisting of tungsten, tantalum, hafnium, molybdenum, niobium, zirconium, vanadium, and titanium. The metalloid may be boron or silicon. The nonmetal may be carbon or nitrogen. The compound may be used, for example, as a barrier material in an integrated circuit.Type: ApplicationFiled: March 31, 2016Publication date: March 21, 2019Applicant: Intel CorporationInventors: Daniel J. Zierath, Jason A. Farmer, Daniel B. Bergstrom
-
Publication number: 20180322994Abstract: Embodiments of the disclosure are directed to a magnetic tunneling junction (MTJ) that includes a diffusion barrier. The diffusion barrier can be disposed between two ferromagnetic layers of the MTJ. More specifically, the diffusion barrier can be disposed between a first ferromagnetic layer, which is adjacent to a natural antiferromagnetic layer, and a second ferromagnetic layer; the first and second ferromagnetic layers and the diffusion barrier being part of a synthetic antiferromagnet. The diffusion barrier can be made of a refractory metal, such as tantalum. The diffusion barrier acts as a barrier for manganese diffusion from the natural antiferromagnetic layer into the synthetic antiferromagnet and other higher layers of the MTJ.Type: ApplicationFiled: December 7, 2015Publication date: November 8, 2018Applicant: Intel CorporationInventors: Tofizur RAHMAN, Christopher J. WIEGAND, Daniel B. BERGSTROM
-
Patent number: 10096513Abstract: An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.Type: GrantFiled: June 9, 2017Date of Patent: October 9, 2018Assignee: Intel CorporationInventors: Jason A. Farmer, Jeffrey S. Leib, Daniel B. Bergstrom
-
Patent number: 10020375Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: October 6, 2017Date of Patent: July 10, 2018Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
-
Publication number: 20180151423Abstract: In one embodiment, a conductive connector for a microelectronic component may be formed with a noble metal layer, acting as an adhesion/wetting layer, disposed between a barrier liner and a conductive fill material. In a further embodiment, the conductive connector may have a noble metal conductive fill material disposed directly on the barrier liner. The use of a noble metal as an adhesion/wetting layer or as a conductive fill material may improve gapfill and adhesion, which may result in the conductive connector being substantially free of voids, thereby improving the electrical performance of the conductive connector relative to conductive connectors without a noble metal as the adhesion/wetting layer or the conductive fill material.Type: ApplicationFiled: June 3, 2015Publication date: May 31, 2018Inventors: Christopher J. Jezewski, Srijit Mukherjee, Daniel B. Bergstrom, Tejaswi K. Indukuri, Flavio Griggio, Ramanan V. Chebiam, James S. Clarke
-
Publication number: 20180047825Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: ApplicationFiled: October 6, 2017Publication date: February 15, 2018Applicant: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
-
Publication number: 20180005841Abstract: Technologies for selectively etching oxide and nitride materials on a work piece are described. Such technologies include methods for etching a work piece with a remote plasma that is produced by igniting a plasma gas flow. By controlling the flow rate of various components of the plasma gas flow, plasmas exhibiting desired etching characteristics may be obtained. Such plasmas may be used in single or multistep etching operations, such as recess etching operations that may be used in the production of non-planar microelectronic devices.Type: ApplicationFiled: September 18, 2017Publication date: January 4, 2018Applicant: Intel CorporationInventors: Jason A. Farmer, Gopinath Trichy, Justin S. Sandford, Daniel B. Bergstrom
-
Patent number: 9812546Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: January 9, 2017Date of Patent: November 7, 2017Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
-
Publication number: 20170278748Abstract: An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.Type: ApplicationFiled: June 9, 2017Publication date: September 28, 2017Applicant: Intel CorporationInventors: JASON A. FARMER, JEFFREY S. LEIB, DANIEL B. BERGSTROM
-
Patent number: 9711399Abstract: An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.Type: GrantFiled: December 26, 2013Date of Patent: July 18, 2017Assignee: Intel CorporationInventors: Jason A. Farmer, Jeffrey S. Leib, Daniel B. Bergstrom
-
Patent number: 9637810Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: September 21, 2015Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu