Abstract: A circuit is designed with a clock circuit (215, 217) coupled to receive a control signal having a first logic state and a second logic state. The clock circuit produces a first clock signal (CLK) response to the first logic state and a second clock signal (*CLK) in response to the second logic state. The second clock signal has a frequency at least twice a frequency of the first clock signal. An address counter (221) is coupled to receive one of the first and second clock signals. The address counter produces a sequence of address signals corresponding to the one of the first and second clock signals. An array of memory cells is arranged to produce a sequence of data bits corresponding to the sequence of address signals. A logic circuit (235, 239, 240) is coupled to receive the sequence of data bits. The logic circuit produces a logical combination of the sequence of data bits.

Abstract: A two stage input buffer substantially reduces propagation delay by triggering only off of the rising edge of the external clock signal, eliminating a pulse generator, and setting the pulse width via feedback through a fixed delay. An unbalanced driver reduces capacitance on the N-channel transistor. In a memory application, such as in a synchronous dynamic random access memory, access time is improved, margin is advantageously added to the hold time requirement, and driver fan out capabilities are improved.