Patents by Inventor Daniel Bensahel

Daniel Bensahel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9356094
    Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: May 31, 2016
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Patent number: 8906776
    Abstract: A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Bensahel, Aomar Halimaoui
  • Publication number: 20130264678
    Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.
    Type: Application
    Filed: May 31, 2013
    Publication date: October 10, 2013
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Patent number: 8536027
    Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: September 17, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Patent number: 8263965
    Abstract: A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: September 11, 2012
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Yves Campidelli, Oliver Kermarrec, Daniel Bensahel
  • Publication number: 20120094470
    Abstract: A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.
    Type: Application
    Filed: September 22, 2011
    Publication date: April 19, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Bensahel, Aomar Halimaoui
  • Patent number: 8049224
    Abstract: Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: November 1, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Daniel Bensahel, Thomas Skotnicki
  • Publication number: 20110108801
    Abstract: A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.
    Type: Application
    Filed: January 11, 2011
    Publication date: May 12, 2011
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Daniel Bensahel, Yves Campidelli, Olivier Kermarrec
  • Patent number: 7884352
    Abstract: The invention relates to a single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: February 8, 2011
    Assignees: STMicroelectronics S.A., STMicroelectronics Crolles 2 SAS
    Inventors: Daniel Bensahel, Yves Campidelli, Oliver Kermarrec
  • Patent number: 7879679
    Abstract: A method for manufacturing an electronic component on a semiconductor substrate, including forming at least one opening in the substrate; forming in the bottom and on the walls of the opening and on the substrate an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and the substrate; trimming the layer portions of the first material and of the second material which are not located in the opening; selectively etching a portion of the first material to obtain trenches; and filling the trenches with at least one third material.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: February 1, 2011
    Assignee: STMicroelectronics Crolles 2 SAS
    Inventors: Oliver Kermarrec, Daniel Bensahel, Yves Campidelli
  • Publication number: 20100314628
    Abstract: Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.
    Type: Application
    Filed: August 24, 2010
    Publication date: December 16, 2010
    Inventors: Bruno Ghyselen, Daniel Bensahel, Thomas Skotnicki
  • Patent number: 7803694
    Abstract: Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: September 28, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Daniel Bensahel, Thomas Skotnicki
  • Patent number: 7534701
    Abstract: A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: May 19, 2009
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Daniel Bensahel, Thomas Skotnicki
  • Publication number: 20080265261
    Abstract: Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.
    Type: Application
    Filed: July 10, 2008
    Publication date: October 30, 2008
    Inventors: Bruno Ghyselen, Daniel Bensahel, Thomas Skotnicki
  • Publication number: 20080239625
    Abstract: A method for manufacturing an electronic component on a semiconductor substrate, including forming at least one opening in the substrate; forming in the bottom and on the walls of the opening and on the substrate an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and the substrate; trimming the layer portions of the first material and of the second material which are not located in the opening; selectively etching a portion of the first material to obtain trenches; and filling the trenches with at least one third material.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 2, 2008
    Applicant: STMicroelectronics Crolles 2 SAS
    Inventors: Oliver Kermarrec, Daniel Bensahel, Yves Campidelli
  • Publication number: 20080164492
    Abstract: A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness.
    Type: Application
    Filed: February 29, 2008
    Publication date: July 10, 2008
    Inventors: Bruno Ghyselen, Daniel Bensahel, Thomas Skotnicki
  • Patent number: 7381267
    Abstract: A method for forming, by epitaxy, a heteroatomic single-crystal semiconductor layer on a single-crystal semiconductor wafer, the crystal lattices of the layer and of the wafer being different, including forming, before the epitaxy, in the wafer surface, at least one ring of discontinuities around a useful region.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: June 3, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Daniel Bensahel, Olivier Kermarrec, Yves Morand, Yves Campidelli, Vincent Cosnier
  • Patent number: 7338883
    Abstract: The invention relates to a process for producing an electronic structure that includes a thin layer of strained semiconductor material from a donor wafer. The donor wafer has a lattice parameter matching layer that includes an upper layer of a semiconductor material having a first lattice parameter and a film of semiconductor material having a second, nominal, lattice parameter that is substantially different from the first lattice parameter and that is strained by the matching layer. This process includes transfer of the film to a receiving substrate. The invention also relates to the semiconductor structures that can be produced by the process.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: March 4, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Daniel Bensahel, Thomas Skotnicki
  • Publication number: 20070248818
    Abstract: The invention relates to a single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism
    Type: Application
    Filed: December 16, 2004
    Publication date: October 25, 2007
    Applicant: STMicroelectronics S.A.
    Inventors: Daniel Bensahel, Yves Campidelli, Olivier Kermarrec
  • Patent number: 7279404
    Abstract: A process for fabricating a strained layer of silicon or of a silicon/germanium alloy, includes: a) the formation of a layer (2) of silicon or of a silicon/germanium alloy on a layer (1) of a material having a modifiable lattice parameter; and b) the modification of the lattice parameter.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: October 9, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Aomar Halimaoui, Daniel Bensahel