Patents by Inventor Daniel C. Worledge

Daniel C. Worledge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11569439
    Abstract: A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 31, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel C. Worledge
  • Patent number: 11527707
    Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 13, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen L. Brown, Guohan Hu, Jonathan Z. Sun, Daniel C. Worledge
  • Patent number: 11417837
    Abstract: A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: August 16, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel C. Worledge
  • Patent number: 11309488
    Abstract: A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 19, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel C. Worledge
  • Patent number: 11223010
    Abstract: Techniques relate to forming a magnetic tunnel junction (MTJ). A synthetic antiferromagnetic reference layer is adjacent to a tunnel barrier layer. The synthetic antiferromagnetic reference layer includes a first magnetic layer, a second magnetic layer, and a reference spacer layer sandwiched between the first magnetic layer and the second magnetic layer. A magnetic free layer is adjacent to the tunnel barrier layer so as to be opposite the synthetic antiferromagnetic reference layer. The synthetic antiferromagnetic reference layer has a thickness of at least one of 3 nanometers (nm), 4 nm, and 3-4 nm.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guohan Hu, Younghyun Kim, Daniel C. Worledge
  • Patent number: 11164615
    Abstract: A magneto-resistance random access memory (MRAM) cell includes a transistor, a wire and a magnetic tunnel junction (MTJ). The MTJ includes a fixed layer of fixed magnetic polarity electrically connected with the transistor, a free layer of variable magnetic polarity electrically connected with the wire and an insulator between the fixed and free layers. First current passed through the wire destabilizes the variable magnetic polarity of the free layer. Second current passed through the transistor in one of two directions during first current passage through the wire directs the variable magnetic polarity of the free layer toward a parallel or anti-parallel condition with respect to the fixed magnetic polarity of the fixed layer. A ceasing of the first current prior to a ceasing of the second current sets the variable magnetic polarity of the free layer in the parallel or anti-parallel condition.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luqiao Liu, Jonathan Z. Sun, Daniel C. Worledge
  • Patent number: 10734571
    Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Joel D. Chudow, Daniel C. Worledge
  • Publication number: 20200083438
    Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 12, 2020
    Inventors: Stephen L. Brown, Guohan Hu, Jonathan Z. Sun, Daniel C. Worledge
  • Patent number: 10553781
    Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen L. Brown, Guohan Hu, Jonathan Z. Sun, Daniel C. Worledge
  • Patent number: 10510391
    Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: December 17, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Guohan Hu, Jeong-Heon Park, Daniel C. Worledge
  • Patent number: 10510390
    Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: December 17, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Guohan Hu, Jeong-Heon Park, Daniel C. Worledge
  • Patent number: 10453509
    Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guohan Hu, Daniel C. Worledge
  • Patent number: 10437665
    Abstract: A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: October 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John K. DeBrosse, Daniel C. Worledge
  • Patent number: 10424727
    Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael C. Gaidis, Janusz J. Nowak, Daniel C. Worledge
  • Publication number: 20190288186
    Abstract: Techniques relate to forming a magnetic tunnel junction (MTJ). A synthetic antiferromagnetic reference layer is adjacent to a tunnel barrier layer. The synthetic antiferromagnetic reference layer includes a first magnetic layer, a second magnetic layer, and a reference spacer layer sandwiched between the first magnetic layer and the second magnetic layer. A magnetic free layer is adjacent to the tunnel barrier layer so as to be opposite the synthetic antiferromagnetic reference layer. The synthetic antiferromagnetic reference layer has a thickness of at least one of 3 nanometers (nm), 4 nm, and 3-4 nm.
    Type: Application
    Filed: May 13, 2019
    Publication date: September 19, 2019
    Inventors: Guohan Hu, Younghyun Kim, Daniel C. Worledge
  • Patent number: 10394647
    Abstract: A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John K. DeBrosse, Daniel C. Worledge
  • Publication number: 20190244647
    Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Guohan Hu, Daniel C. Worledge
  • Patent number: 10374145
    Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen L. Brown, Guohan Hu, Jonathan Z. Sun, Daniel C. Worledge
  • Patent number: 10361361
    Abstract: Techniques relate to forming a magnetic tunnel junction (MTJ). A synthetic antiferromagnetic reference layer is adjacent to a tunnel barrier layer. The synthetic antiferromagnetic reference layer includes a first magnetic layer, a second magnetic layer, and a reference spacer layer sandwiched between the first magnetic layer and the second magnetic layer. A magnetic free layer is adjacent to the tunnel barrier layer so as to be opposite the synthetic antiferromagnetic reference layer. The synthetic antiferromagnetic reference layer has a thickness of at least one of 3 nanometers (nm), 4 nm, and 3-4 nm.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: July 23, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Guohan Hu, Younghyun Kim, Daniel C. Worledge
  • Publication number: 20190221738
    Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.
    Type: Application
    Filed: March 26, 2019
    Publication date: July 18, 2019
    Inventors: MICHAEL C. GAIDIS, JANUSZ J. NOWAK, DANIEL C. WORLEDGE